From patchwork Tue May 21 06:35:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 245205 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4D9C82C00AA for ; Tue, 21 May 2013 16:40:32 +1000 (EST) Received: from localhost ([::1]:60650 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegFK-0005CA-BH for incoming@patchwork.ozlabs.org; Tue, 21 May 2013 02:40:30 -0400 Received: from eggs.gnu.org ([208.118.235.92]:52693) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegF3-00056f-8I for qemu-devel@nongnu.org; Tue, 21 May 2013 02:40:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UegF1-0006Qh-W0 for qemu-devel@nongnu.org; Tue, 21 May 2013 02:40:13 -0400 Received: from mail-da0-x236.google.com ([2607:f8b0:400e:c00::236]:56001) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegF1-0006QT-J0 for qemu-devel@nongnu.org; Tue, 21 May 2013 02:40:11 -0400 Received: by mail-da0-f54.google.com with SMTP id z17so204751dal.27 for ; Mon, 20 May 2013 23:40:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=VRHYNid/Cx3mw/DjZZsefHdqXi7tcjMLWGl7aMnAHpg=; b=AtyFtY72sFRoSzaqmVfPTJeMYmzhpiMVM+kY7zPWHXtg05z81JGVmA0P/8g+6Pte51 uD2I5Neh3uNYqwBbxuT3X8f13O5KThYuQ0Xg2Z2m2ZZqHC1kh2AbW635ZT5iQYyPxnIV dgjk8c7Q2Ym3xzOkK/V7NOTANzaTfOGPdDAAmIo16pAE56Ur6RUt9wL30Zyj/3O+AN/J NsyKqlqr6As5dSFy2haKlpY1JDDcpDDo2rxRqhnLr7cHfIJuid0we8iBl48sLKL/C4F+ IFOVHtFVbTzVtw4XjNzv7+KiPnbQVYCC1W3XNhQyVQ4Xzop953erULtWI9GRX2cSGbQH oPlA== X-Received: by 10.66.9.99 with SMTP id y3mr1635777paa.189.1369118410625; Mon, 20 May 2013 23:40:10 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id l4sm1490212pbo.6.2013.05.20.23.40.07 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 20 May 2013 23:40:09 -0700 (PDT) From: peter.crosthwaite@xilinx.com To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Tue, 21 May 2013 16:35:52 +1000 Message-Id: X-Mailer: git-send-email 1.8.3.rc1.44.gb387c77.dirty In-Reply-To: References: X-Gm-Message-State: ALoCoQmY8OqluhB3BXMXhrbcDk36YfzbfB3OsCaX30oQ9PVLtzfyXDV3xxlV7K0FTgri/WX/dlPw X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c00::236 Cc: edgar.iglesias@gmail.com Subject: [Qemu-devel] [PATCH arm-devs v4 10/15] xilinx_spips: Fix CTRL register RW bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite The CTRL register was RAZ/WI on some of the RW bits. Even though the function behind these bits is invalid in QEMU, they should still be guest accessible. Fix. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- changed from v1 Macroified magic number (PMM review) hw/ssi/xilinx_spips.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index ea8a593..3e9e76c 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -56,6 +56,7 @@ #define CLK_PH (1 << 2) #define CLK_POL (1 << 1) #define MODE_SEL (1 << 0) +#define R_CONFIG_RSVD (0x7bf40000) /* interrupt mechanism */ #define R_INTR_STATUS (0x04 / 4) @@ -355,7 +356,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, addr >>= 2; switch (addr) { case R_CONFIG: - mask = 0x0002FFFF; + mask = ~(R_CONFIG_RSVD | MAN_START_COM); break; case R_INTR_STATUS: ret = s->regs[addr] & IXR_ALL; @@ -415,7 +416,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, addr >>= 2; switch (addr) { case R_CONFIG: - mask = 0x0002FFFF; + mask = ~(R_CONFIG_RSVD | MAN_START_COM); if (value & MAN_START_COM) { man_start_com = 1; }