From patchwork Tue May 21 06:32:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 245202 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 48D1F2C00A8 for ; Tue, 21 May 2013 16:37:43 +1000 (EST) Received: from localhost ([::1]:53737 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegCb-0001Ns-1M for incoming@patchwork.ozlabs.org; Tue, 21 May 2013 02:37:41 -0400 Received: from eggs.gnu.org ([208.118.235.92]:52179) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegCG-0001L9-NC for qemu-devel@nongnu.org; Tue, 21 May 2013 02:37:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UegCF-0005EP-4w for qemu-devel@nongnu.org; Tue, 21 May 2013 02:37:20 -0400 Received: from mail-pd0-f174.google.com ([209.85.192.174]:53690) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegCE-0005EB-Ts for qemu-devel@nongnu.org; Tue, 21 May 2013 02:37:19 -0400 Received: by mail-pd0-f174.google.com with SMTP id 14so292314pdj.5 for ; Mon, 20 May 2013 23:37:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=suoMr39jYohHewtMhicsswPSs6bKbuu3AFMkE4le+24=; b=ogB0vNEC73FXI5/TPFsX8bXJgPN24ubGuPKyn2DUa5eJZQcqoDdB29UDYEwTOKoCUL 5KNM1f0hRJ2sDXxr/gKWhZdta1h+V4OtOaaNfPCVdgeiOW0LSoUFv7LE8GGlaKr/MXZY aqhVHCuB016A1wjqcoq7eHhOBLx8qFhlyeuHtiPHQS5te9M2yugsCzRWRvry1EfF4vBm LpvjEYCJtaoNBfU5a8l5JkfZ8bw2in+8krG82EbObeal8hzo551/cPwaOyasZNVd38fu c05b7jhewRUV1Y+Fo8qZlsQORODdJ9AmqYZpdGkV/DF7piazLrlGfkD4Ty2RVpqki9PC mI2w== X-Received: by 10.66.188.137 with SMTP id ga9mr1770283pac.9.1369118238173; Mon, 20 May 2013 23:37:18 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id qb1sm1431081pbb.33.2013.05.20.23.37.15 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 20 May 2013 23:37:17 -0700 (PDT) From: peter.crosthwaite@xilinx.com To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Tue, 21 May 2013 16:32:59 +1000 Message-Id: <677490a6ee1953fe5d366e599d665de645ac84db.1369117359.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.8.3.rc1.44.gb387c77.dirty In-Reply-To: References: X-Gm-Message-State: ALoCoQn2Cz0AKCkfQUG7opQiKiWBosxAsx5tzdtl0HDlTpCMsLFdkywxtKxdU81gkZzQRgPuruo9 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.174 Cc: edgar.iglesias@gmail.com Subject: [Qemu-devel] [PATCH arm-devs v4 06/15] xilinx_spips: Trash LQ page cache on mode change X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite Invalidate the LQSPI cached page when transitioning into LQSPI mode. Otherwise there is a possibility that the controller will return stale data to the guest when transitioning back to LQ_MODE after a page program. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- changed from v2: Removed extraneous break after goto (PMM review) changed from v1: Re-implemented using separate SPI/QSPI write handlers. hw/ssi/xilinx_spips.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 86f33ef..cf4c43e 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -165,6 +165,8 @@ typedef struct { typedef struct XilinxSPIPSClass { SysBusDeviceClass parent_class; + const MemoryRegionOps *reg_ops; + uint32_t rx_fifo_size; uint32_t tx_fifo_size; } XilinxSPIPSClass; @@ -462,6 +464,25 @@ static const MemoryRegionOps spips_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; +static void xilinx_qspips_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + XilinxQSPIPS *q = XILINX_QSPIPS(opaque); + + xilinx_spips_write(opaque, addr, value, size); + addr >>= 2; + + if (addr == R_LQSPI_CFG) { + q->lqspi_cached_addr = ~0ULL; + } +} + +static const MemoryRegionOps qspips_ops = { + .read = xilinx_spips_read, + .write = xilinx_qspips_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + #define LQSPI_CACHE_SIZE 1024 static uint64_t @@ -565,7 +586,7 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp) sysbus_init_irq(sbd, &s->cs_lines[i]); } - memory_region_init_io(&s->iomem, &spips_ops, s, "spi", R_MAX*4); + memory_region_init_io(&s->iomem, xsc->reg_ops, s, "spi", R_MAX*4); sysbus_init_mmio(sbd, &s->iomem); s->irqline = -1; @@ -629,6 +650,7 @@ static void xilinx_qspips_class_init(ObjectClass *klass, void * data) XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); dc->realize = xilinx_qspips_realize; + xsc->reg_ops = &qspips_ops; xsc->rx_fifo_size = RXFF_A_Q; xsc->tx_fifo_size = TXFF_A_Q; } @@ -643,6 +665,7 @@ static void xilinx_spips_class_init(ObjectClass *klass, void *data) dc->props = xilinx_spips_properties; dc->vmsd = &vmstate_xilinx_spips; + xsc->reg_ops = &spips_ops; xsc->rx_fifo_size = RXFF_A; xsc->tx_fifo_size = TXFF_A; }