From patchwork Tue May 21 06:30:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 245199 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3C14E2C00AE for ; Tue, 21 May 2013 16:36:09 +1000 (EST) Received: from localhost ([::1]:49049 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegB5-0007GI-FB for incoming@patchwork.ozlabs.org; Tue, 21 May 2013 02:36:07 -0400 Received: from eggs.gnu.org ([208.118.235.92]:51674) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegAA-0006cA-UM for qemu-devel@nongnu.org; Tue, 21 May 2013 02:35:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UegA9-0004bS-Oa for qemu-devel@nongnu.org; Tue, 21 May 2013 02:35:10 -0400 Received: from mail-pd0-f175.google.com ([209.85.192.175]:51404) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UegA9-0004bC-IZ for qemu-devel@nongnu.org; Tue, 21 May 2013 02:35:09 -0400 Received: by mail-pd0-f175.google.com with SMTP id y14so292547pdi.20 for ; Mon, 20 May 2013 23:35:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=MJsAkSYY/FTJb2HlD+vo6tzUg/EuYQcssK7RJqMJc9k=; b=dUsPM4xl70pIf9pHnVduaZWjC0FVMyRJz29PkX0bh4uYRbf29zQDskqCAFnaeF6ix6 UYA1ZSA7Efrf25fvufeRohQdx37lq1Dpy63g32A2pDV8ZIhjlEIz7KCEN2KGSoeYkC/i bZKSx+tj6h3ALN6jj6DAPmL2cKYKWRJDE/7+XS8l8K2inhJRh3604YVp0VEyf8YA7rwy HU5Y3nyLEJfdl7AVr/mahPYyXZtp59GNFxhC1XOZLyDfuF8gX/SQYhEZJ3fEuNMYS9Om FEmdgF3OVh+cxW/DcX7qeaiiKGFnNLwelILFxY8GBcCF81wFo5LkezZZRsUMkG8EgPOV xwaA== X-Received: by 10.66.245.110 with SMTP id xn14mr1633226pac.130.1369118108814; Mon, 20 May 2013 23:35:08 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id zo4sm1443767pbc.21.2013.05.20.23.35.05 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 20 May 2013 23:35:07 -0700 (PDT) From: peter.crosthwaite@xilinx.com To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Tue, 21 May 2013 16:30:50 +1000 Message-Id: X-Mailer: git-send-email 1.8.3.rc1.44.gb387c77.dirty In-Reply-To: References: X-Gm-Message-State: ALoCoQkftq8qlUP+82ECn5PszraNa1CM2ZcEexd/igV5e9M8yn5tzzAiDnh3xmtI6SJecLUNDX8z X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.175 Cc: edgar.iglesias@gmail.com Subject: [Qemu-devel] [PATCH arm-devs v4 03/15] xilinx_spips: Inhibit interrupts in LQSPI mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite The real hardware does not produce interrupts in LQSPI mode. Inhibit generation of interrupts when the LQ_MODE bit is set. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- hw/ssi/xilinx_spips.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 261d948..a8691d5 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -204,6 +204,9 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) static void xilinx_spips_update_ixr(XilinxSPIPS *s) { + if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { + return; + } /* These are set/cleared as they occur */ s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW | IXR_TX_FIFO_MODE_FAIL); @@ -256,7 +259,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) for (i = 0; i < num_effective_busses(s); ++i) { if (!i || s->snoop_state == SNOOP_STRIPING) { if (fifo8_is_empty(&s->tx_fifo)) { - s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; + if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { + s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; + } xilinx_spips_update_ixr(s); return; } else {