Patchwork [AArch64] Support BFI instruction and insv standard pattern

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Submitter Ian Bolton
Date May 20, 2013, 6:55 p.m.
Message ID <000401ce558b$9a28bfe0$ce7a3fa0$@bolton@arm.com>
Download mbox | patch
Permalink /patch/245091/
State New
Headers show

Comments

Ian Bolton - May 20, 2013, 6:55 p.m.
> Hi,
> 
> This patch implements the BFI variant of BFM.  In doing so, it also
> implements the insv standard pattern.
> 
> I've regression tested on bare-metal and linux.
> 
> It comes complete with its own compilation and execution testcase.
> 
> OK for trunk?
> 
> Cheers,
> Ian
> 
> 
> 2013-05-08  Ian Bolton  <ian.bolton@arm.com>
> 
> gcc/
> 	* config/aarch64/aarch64.md (insv): New define_expand.
> 	(*insv_reg<mode>): New define_insn.
> 
> testsuite/
> 	* gcc.target/aarch64/bfm_1.c: New test.


(This patch did not yet get commit approval.)

I improved this patch during the work I did on the recent insv_imm patch
(http://gcc.gnu.org/ml/gcc-patches/2013-05/msg01007.html).

I also renamed the testcase.

Regression testing completed successfully.

OK for trunk?

Cheers,
Ian


2013-05-20  Ian Bolton  <ian.bolton@arm.com>

gcc/
	* config/aarch64/aarch64.md (insv): New define_expand.
	(*insv_reg<mode>): New define_insn.

testsuite/
	* gcc.target/aarch64/insv_1.c: New test.
Richard Henderson - May 20, 2013, 7:36 p.m.
On 05/20/2013 11:55 AM, Ian Bolton wrote:
> I improved this patch during the work I did on the recent insv_imm patch
> (http://gcc.gnu.org/ml/gcc-patches/2013-05/msg01007.html).

Thanks, you cleaned up almost everything on which I would have commented
with the previous patch revision.  The only thing left is:

> +  else if (!register_operand (value, <MODE>mode))
> +    operands[3] = force_reg (<MODE>mode, value);

Checking register_operand before force_reg is unnecessary; you're not saving a
function call, and force_reg will itself perform the register check.


r~

Patch

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index b27bcda..e5d6950 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3164,6 +3164,52 @@ 
    (set_attr "mode" "<MODE>")]
 )
 
+;; Bitfield Insert (insv)
+(define_expand "insv<mode>"
+  [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand")
+			  (match_operand 1 "const_int_operand")
+			  (match_operand 2 "const_int_operand"))
+	(match_operand:GPI 3 "general_operand"))]
+  ""
+{
+  unsigned HOST_WIDE_INT width = UINTVAL (operands[1]);
+  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
+  rtx value = operands[3];
+
+  if (width == 0 || (pos + width) > GET_MODE_BITSIZE (<MODE>mode))
+    FAIL;
+
+  if (CONST_INT_P (value))
+    {
+      unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
+
+      /* Prefer AND/OR for inserting all zeros or all ones.  */
+      if ((UINTVAL (value) & mask) == 0
+	   || (UINTVAL (value) & mask) == mask)
+	FAIL;
+
+      /* Force the constant into a register, unless this is a 16-bit aligned
+	 16-bit wide insert, which is handled by insv_imm.  */
+      if (width != 16 || (pos % 16) != 0)
+	operands[3] = force_reg (<MODE>mode, value);
+    }
+  else if (!register_operand (value, <MODE>mode))
+    operands[3] = force_reg (<MODE>mode, value);
+})
+
+(define_insn "*insv_reg<mode>"
+  [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r")
+			  (match_operand 1 "const_int_operand" "n")
+			  (match_operand 2 "const_int_operand" "n"))
+	(match_operand:GPI 3 "register_operand" "r"))]
+  "!(UINTVAL (operands[1]) == 0
+     || (UINTVAL (operands[2]) + UINTVAL (operands[1])
+	 > GET_MODE_BITSIZE (<MODE>mode)))"
+  "bfi\\t%<w>0, %<w>3, %2, %1"
+  [(set_attr "v8type" "bfm")
+   (set_attr "mode" "<MODE>")]
+)
+
 (define_insn "*<optab><ALLX:mode>_shft_<GPI:mode>"
   [(set (match_operand:GPI 0 "register_operand" "=r")
 	(ashift:GPI (ANY_EXTEND:GPI
diff --git a/gcc/testsuite/gcc.target/aarch64/insv_1.c b/gcc/testsuite/gcc.target/aarch64/insv_1.c
new file mode 100644
index 0000000..0977e15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/insv_1.c
@@ -0,0 +1,84 @@ 
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+typedef struct bitfield
+{
+  unsigned short eight: 8;
+  unsigned short four: 4;
+  unsigned short five: 5;
+  unsigned short seven: 7;
+  unsigned int sixteen: 16;
+} bitfield;
+
+bitfield
+bfi1 (bitfield a)
+{
+  /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 0, 8" } } */
+  a.eight = 3;
+  return a;
+}
+
+bitfield
+bfi2 (bitfield a)
+{
+  /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 16, 5" } } */
+  a.five = 7;
+  return a;
+}
+
+bitfield
+movk (bitfield a)
+{
+  /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x1d6b, lsl 32" } } */
+  a.sixteen = 7531;
+  return a;
+}
+
+bitfield
+set1 (bitfield a)
+{
+  /* { dg-final { scan-assembler "orr\tx\[0-9\]+, x\[0-9\]+, 2031616" } } */
+  a.five = 0x1f;
+  return a;
+}
+
+bitfield
+set0 (bitfield a)
+{
+  /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -2031617" } } */
+  a.five = 0;
+  return a;
+}
+
+
+int
+main (int argc, char** argv)
+{
+  static bitfield a;
+  bitfield b = bfi1 (a);
+  bitfield c = bfi2 (b);
+  bitfield d = movk (c);
+
+  if (d.eight != 3)
+    abort ();
+
+  if (d.five != 7)
+    abort ();
+
+  if (d.sixteen != 7531)
+    abort ();
+
+  d = set1 (d);
+  if (d.five != 0x1f)
+    abort ();
+
+  d = set0 (d);
+  if (d.five != 0)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */