From patchwork Mon Mar 16 15:52:09 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Jander X-Patchwork-Id: 24502 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 1DEFFDE33E for ; Tue, 17 Mar 2009 02:52:33 +1100 (EST) X-Original-To: linuxppc-dev@ozlabs.org Delivered-To: linuxppc-dev@ozlabs.org Received: from protonic.prtnl (protonic.xs4all.nl [213.84.116.84]) by ozlabs.org (Postfix) with ESMTP id 92591DDFAE for ; Tue, 17 Mar 2009 02:52:11 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by protonic.prtnl (Postfix) with ESMTP id CB43229EC9; Mon, 16 Mar 2009 16:50:51 +0100 (CET) Received: from protonic.prtnl ([127.0.0.1]) by localhost (protonic [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 20404-09; Mon, 16 Mar 2009 16:50:51 +0100 (CET) Received: from archvile.prtnl (archvile.prtnl [192.168.1.153]) by protonic.prtnl (Postfix) with ESMTP id 915E829EBA; Mon, 16 Mar 2009 16:50:51 +0100 (CET) From: David Jander Organization: Protonic Holland To: Kumar Gala Subject: [RFC][PATCH v5] MPC5121 TLB errata workaround Date: Mon, 16 Mar 2009 16:52:09 +0100 User-Agent: KMail/1.9.10 MIME-Version: 1.0 Content-Disposition: inline Message-Id: <200903161652.09747.david.jander@protonic.nl> X-Virus-Scanned: by amavisd-new at prtnl Cc: linuxppc-dev@ozlabs.org, Paul Mackerras , Wolfgang Denk , gunnar@genesi-usa.com X-BeenThere: linuxppc-dev@ozlabs.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org Complete workaround for DTLB errata in e300c2/c3/c4 processors. Due to the bug, the hardware-implemented LRU algorythm always goes to way 1 of the TLB. This fix implements the proposed software workaround in form of a LRW table for chosing the TLB-way. Signed-off-by: Kumar Gala Signed-off-by: David Jander Acked-by: Kenneth Johansson diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index 0f4fac5..3971ee4 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -578,9 +578,21 @@ DataLoadTLBMiss: andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ mtspr SPRN_RPA,r1 mfspr r3,SPRN_DMISS + mfspr r2,SPRN_SRR1 /* Need to restore CR0 */ + mtcrf 0x80,r2 +#ifdef CONFIG_PPC_MPC512x + li r0,1 + mfspr r1,SPRN_SPRG6 + rlwinm r2,r3,17,27,31 /* Get Address bits 19:15 */ + slw r0,r0,r2 + xor r1,r0,r1 + srw r0,r1,r2 + mtspr SPRN_SPRG6,r1 + mfspr r2,SPRN_SRR1 + rlwimi r2,r0,31-14,14,14 + mtspr SPRN_SRR1,r2 +#endif tlbld r3 - mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ - mtcrf 0x80,r3 rfi DataAddressInvalid: mfspr r3,SPRN_SRR1 @@ -646,9 +658,21 @@ DataStoreTLBMiss: andc r1,r3,r1 /* PP = user? 2: 0 */ mtspr SPRN_RPA,r1 mfspr r3,SPRN_DMISS + mfspr r2,SPRN_SRR1 /* Need to restore CR0 */ + mtcrf 0x80,r2 +#ifdef CONFIG_PPC_MPC512x + li r0,1 + mfspr r1,SPRN_SPRG6 + rlwinm r2,r3,17,27,31 /* Get Address bits 19:15 */ + slw r0,r0,r2 + xor r1,r0,r1 + srw r0,r1,r2 + mtspr SPRN_SPRG6,r1 + mfspr r2,SPRN_SRR1 + rlwimi r2,r0,31-14,14,14 + mtspr SPRN_SRR1,r2 +#endif tlbld r3 - mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ - mtcrf 0x80,r3 rfi #ifndef CONFIG_ALTIVEC