From patchwork Sun May 19 15:59:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steven Bosscher X-Patchwork-Id: 244817 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 129562C0099 for ; Mon, 20 May 2013 02:01:15 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=u/CGE2rImN0LpXp7myPaLBYMQBNCgFPGKbgcUg7/7J0YJZ B8TpCVtMyjwQ0qWEoP0My5LIoJe2ldpcP1NTouo8meo2CWl8YtwdCZbvlteHj3Ub W1WzeofM9Y/+cHnRiTUSoR70Du0m0uJly9hjW5GpknjpUF+C+KxoKrSbZZweI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=UJYTUSKRN4OyHV6XNtrO3PGja9s=; b=Bu4xZnMHH8Lp/4SxYA/N o0u4EEmiU6g9CvL4bdH2sGmFT2OX7ogBX03J4Ht/vQ0X+Ydf0q+vMzabXcZ+tw5r b6t/eE+e5D7Lt1KO+sM4ubDs6nTq0cVO0LHalTvQMcDdOeDNjhWIP2mqHcuI2tgB FgTCMykgfEnxEOKP5iUcqMU= Received: (qmail 32766 invoked by alias); 19 May 2013 16:01:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 32743 invoked by uid 89); 19 May 2013 16:01:07 -0000 X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, RCVD_IN_HOSTKARMA_YE, SPF_PASS, TW_CF, TW_EG, TW_HW autolearn=ham version=3.3.1 Received: from mail-vb0-f43.google.com (HELO mail-vb0-f43.google.com) (209.85.212.43) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Sun, 19 May 2013 16:00:37 +0000 Received: by mail-vb0-f43.google.com with SMTP id p14so3287308vbm.16 for ; Sun, 19 May 2013 09:00:35 -0700 (PDT) X-Received: by 10.220.168.202 with SMTP id v10mr32565726vcy.71.1368979235487; Sun, 19 May 2013 09:00:35 -0700 (PDT) MIME-Version: 1.0 Received: by 10.58.50.40 with HTTP; Sun, 19 May 2013 08:59:55 -0700 (PDT) From: Steven Bosscher Date: Sun, 19 May 2013 17:59:55 +0200 Message-ID: Subject: [patch] Preserve the CFG until after final To: GCC Patches X-Virus-Found: No Hello, This patch allows targets to keep the CFG around until after final, by skipping pass_free_cfg and CFG-destructive passes like dbr_schedule, and by making insn splitting before 'final' use split_all_insns instead of split_all_insns_noflow if pass_free_cfg was skipped. Most machine reorg passes also are not able to maintain the CFG, so I've split the machine_reorg hook into separate CFG-aware and CFG-unaware versions, renaming the existing hook (to signal that maintaining the CFG is desirable in new ports ;-). For the moment, only ix86 uses the CFG-aware version of the hook, but there are a handful of targets that can be converted to do this also (ia64, bfin, c6x, sparc, probably others). Other ports can change to the CFG-aware machine reorg pass and keep part of the current, non CFG-aware reorg pass for the second hook (mips). Some ports have CFG-aware machine-reorg passes but verify_flow_info fails after the machine-reorg pass because the port emits insns between basic blocks, e.g. for const pools. What's missing is a way for verify_flow_info to be tolerant of such non-insns but I'm not sure yet what the best approach for this will be (possibilities I've considered so far are: allow bare UNSPECV insns between basic blocks after machine-reorg; put a flag on such non-insns; maintain a bitmap of uids for non-insns; ...). I hope that maintainers will over time change their machine reorgs to maintain the CFG, so that passes like pass_dwarf2_frame can use the CFG instead of creating "a facsimile of one on the fly" (see dwarf2cfi.c). Bootstrapped&tested on x86_64-unknown-linux-gnu (unix{,-m32}). OK for trunk? Ciao! Steven * target.def (machine_dependent_reorg): Add documentation. (machine_dependent_reorg_nocfg): New hook. * doc/tm.texi.in (TARGET_MACHINE_DEPENDENT_REORG): Remove old documentation. (TARGET_MACHINE_DEPENDENT_REORG_NOCFG): New hook insert point. * doc/tm.texi: Regenerate * function.h (struct rtl_data): Add 'cfg_released' member. * cfgrtl.c (rest_of_pass_free_cfg): Set it at the end. * tree-pass.h (pass_cfg_unaware_passes, pass_machine_reorg_nocfg): New passes. * passes.c (init_optimization_passes): Schedule the new passes. Use pass_machine_reorg_nocfg to group passes that do not maintain the control flow graph. * reorg.c (gate_handle_machine_reorg_nocfg): New function. (rest_of_handle_machine_reorg_nocfg): New Function. (gate_cfg_unaware_passes): New function. (gate_handle_machine_reorg): New function. (rest_of_handle_machine_reorg): New function. (pass_machine_reorg_nocfg): New pass. (pass_cfg_unaware_passes): New pass. * recog.c (rest_of_handle_final_split): New function. (pass_split_for_short): Call rest_of_handle_final_split instead of directly calling split_all_insns_noflow. * sched-ebb.c (schedule_ebbs_init): Do not call compute_bb_for_insn. * config/i386/i386.c (ix86_reorg): Do not call compute_bb_for_insn. * config/alpha/alpha.c: Replace TARGET_MACHINE_DEPENDENT_REORG with TARGET_MACHINE_DEPENDENT_REORG_NOCFG. * config/frv/frv.c: Likewise. * config/s390/s390.c: Likewise. * config/spu/spu.c: Likewise. * config/mep/mep.c; * config/tilegx/tilegx.c: Likewise. * config/sh/sh.c: Likewise. * config/avr/avr.c: Likewise. * config/stormy16/stormy16.c: Likewise. * config/mn10300/mn10300.c: Likewise. * config/c6x/c6x.c: Likewise. * config/ia64/ia64.c: Likewise. * config/picochip/picochip.c: Likewise. * config/mcore/mcore.c: Likewise. * config/tilepro/tilepro.c: Likewise. * config/arm/arm.c: Likewise. * config/pa/pa.c: Likewise. * config/mips/mips.c: Likewise. * config/v850/v850.c: Likewise. * config/h8300/h8300.c: Likewise. * config/mmix/mmix.c: Likewise. * config/bfin/bfin.c: Likewise. Index: target.def =================================================================== --- target.def (revision 199028) +++ target.def (working copy) @@ -1888,11 +1888,37 @@ DEFHOOK enum machine_mode, (enum machine_mode m1, enum machine_mode m2), default_cc_modes_compatible) -/* Do machine-dependent code transformations. Called just before - delayed-branch scheduling. */ +/* Do machine-dependent code transformations. */ DEFHOOK (machine_dependent_reorg, - "", + "If non-null, this hook can be used to perform target-specific passes \ +over the instruction stream near the very end of the compilation of \ +a function. The hook is called via @code{pass_machine_reorg} just \ +before the delayed-branch scheduling pass. This hook is optional, \ +@code{pass_machine_reorg} pass only runs if the hook non-null.\n\ +This target hook should maintain the CFG (@code{verify_flow_inf} \ +should not fail after this pass). Legacy machine dependent reorg \ +passes that destroy the CFG should not define this hook, but instead \ +use tne @code{machine_dependent_reorg_nocfg} hook. \ +\n\ +The hook an be used for various target-specific purposes, such as \ +machine-specific code transformations to work around errata or other \ +hazards, laying out constant pools. The hook can also be used for \ +the implementation of machine-dependent optimizations, although this \ +practice is discouraged if the optimization may be useful for other \ +target machines as well. Such optimizations should be implemented \ +in the compiler midde end.", + void, (void), NULL) + +/* Like machine_dependent_reorg but for legacy machine reorg passes that + are not aware of the CFG. */ +DEFHOOK +(machine_dependent_reorg_nocfg, + "Like @code{machine_dependent_reorg}, but for use by legacy targets. \ +This hook assumes that the machine dependent pass is not aware of \ +the control flow graph and is unable to maintain it properly. Before \ +the hook is called, the control flow graph is released. Basic blocks \ +still exist but @code{BLOCK_FOR_INSN} will be nullified.", void, (void), NULL) /* Create the __builtin_va_list type. */ Index: doc/tm.texi.in =================================================================== --- doc/tm.texi.in (revision 199028) +++ doc/tm.texi.in (working copy) @@ -10707,18 +10707,8 @@ to by @var{ce_info}. @end defmac @hook TARGET_MACHINE_DEPENDENT_REORG -If non-null, this hook performs a target-specific pass over the -instruction stream. The compiler will run it at all optimization levels, -just before the point at which it normally does delayed-branch scheduling. -The exact purpose of the hook varies from target to target. Some use -it to do transformations that are necessary for correctness, such as -laying out in-function constant pools or avoiding hardware hazards. -Others use it as an opportunity to do some machine-dependent optimizations. - -You need not implement the hook if it has nothing to do. The default -definition is null. -@end deftypefn +@hook TARGET_MACHINE_DEPENDENT_REORG_NOCFG @hook TARGET_INIT_BUILTINS Define this hook if you have any machine-specific built-in functions Index: doc/tm.texi =================================================================== --- doc/tm.texi (revision 199028) +++ doc/tm.texi (working copy) @@ -10863,17 +10863,13 @@ to by @var{ce_info}. @end defmac @deftypefn {Target Hook} void TARGET_MACHINE_DEPENDENT_REORG (void) -If non-null, this hook performs a target-specific pass over the -instruction stream. The compiler will run it at all optimization levels, -just before the point at which it normally does delayed-branch scheduling. - -The exact purpose of the hook varies from target to target. Some use -it to do transformations that are necessary for correctness, such as -laying out in-function constant pools or avoiding hardware hazards. -Others use it as an opportunity to do some machine-dependent optimizations. +If non-null, this hook can be used to perform target-specific passes over the instruction stream near the very end of the compilation of a function. The hook is called via @code{pass_machine_reorg} just before the delayed-branch scheduling pass. This hook is optional, @code{pass_machine_reorg} pass only runs if the hook non-null. +This target hook should maintain the CFG (@code{verify_flow_inf} should not fail after this pass). Legacy machine dependent reorg passes that destroy the CFG should not define this hook, but instead use tne @code{machine_dependent_reorg_nocfg} hook. +The hook an be used for various target-specific purposes, such as machine-specific code transformations to work around errata or other hazards, laying out constant pools. The hook can also be used for the implementation of machine-dependent optimizations, although this practice is discouraged if the optimization may be useful for other target machines as well. Such optimizations should be implemented in the compiler midde end. +@end deftypefn -You need not implement the hook if it has nothing to do. The default -definition is null. +@deftypefn {Target Hook} void TARGET_MACHINE_DEPENDENT_REORG_NOCFG (void) +Like @code{machine_dependent_reorg}, but for use by legacy targets. This hook assumes that the machine dependent pass is not aware of the control flow graph and is unable to maintain it properly. Before the hook is called, the control flow graph is released. Basic blocks still exist but @code{BLOCK_FOR_INSN} will be nullified. @end deftypefn @deftypefn {Target Hook} void TARGET_INIT_BUILTINS (void) Index: function.h =================================================================== --- function.h (revision 199028) +++ function.h (working copy) @@ -455,6 +455,9 @@ struct GTY(()) rtl_data { pass. */ bool bb_reorder_complete; + /* Nonzero if pass_free_cfg has run. */ + bool cfg_released; + /* Like regs_ever_live, but 1 if a reg is set or clobbered from an asm. Unlike regs_ever_live, elements of this array corresponding to eliminable regs (like the frame pointer) are set if an asm Index: cfgrtl.c =================================================================== --- cfgrtl.c (revision 199028) +++ cfgrtl.c (working copy) @@ -452,6 +452,7 @@ rest_of_pass_free_cfg (void) #endif free_bb_for_insn (); + crtl->cfg_released = true; return 0; } Index: tree-pass.h =================================================================== --- tree-pass.h (revision 199028) +++ tree-pass.h (working copy) @@ -474,6 +474,8 @@ extern struct rtl_opt_pass pass_duplicat extern struct rtl_opt_pass pass_variable_tracking; extern struct rtl_opt_pass pass_free_cfg; extern struct rtl_opt_pass pass_machine_reorg; +extern struct rtl_opt_pass pass_cfg_unaware_passes; +extern struct rtl_opt_pass pass_machine_reorg_nocfg; extern struct rtl_opt_pass pass_cleanup_barriers; extern struct rtl_opt_pass pass_delay_slots; extern struct rtl_opt_pass pass_split_for_shorten_branches; Index: passes.c =================================================================== --- passes.c (revision 199028) +++ passes.c (working copy) @@ -1659,10 +1659,15 @@ init_optimization_passes (void) NEXT_PASS (pass_compute_alignments); NEXT_PASS (pass_duplicate_computed_gotos); NEXT_PASS (pass_variable_tracking); - NEXT_PASS (pass_free_cfg); NEXT_PASS (pass_machine_reorg); - NEXT_PASS (pass_cleanup_barriers); - NEXT_PASS (pass_delay_slots); + NEXT_PASS (pass_cfg_unaware_passes); + { + struct opt_pass **p = &pass_cfg_unaware_passes.pass.sub; + NEXT_PASS (pass_free_cfg); + NEXT_PASS (pass_machine_reorg_nocfg); + NEXT_PASS (pass_cleanup_barriers); + NEXT_PASS (pass_delay_slots); + } NEXT_PASS (pass_split_for_shorten_branches); NEXT_PASS (pass_convert_to_eh_region_ranges); NEXT_PASS (pass_shorten_branches); Index: reorg.c =================================================================== --- reorg.c (revision 199028) +++ reorg.c (working copy) @@ -3871,15 +3871,83 @@ struct rtl_opt_pass pass_delay_slots = 0 /* todo_flags_finish */ } }; + +/* Machine dependent reorg pass, not CFG aware. */ +static bool +gate_handle_machine_reorg_nocfg (void) +{ + return targetm.machine_dependent_reorg_nocfg != 0; +} + +static unsigned int +rest_of_handle_machine_reorg_nocfg (void) +{ + targetm.machine_dependent_reorg_nocfg (); + return 0; +} + +struct rtl_opt_pass pass_machine_reorg_nocfg = +{ + { + RTL_PASS, + "mach_nocfg", /* name */ + OPTGROUP_NONE, /* optinfo_flags */ + gate_handle_machine_reorg_nocfg, /* gate */ + rest_of_handle_machine_reorg_nocfg, /* execute */ + NULL, /* sub */ + NULL, /* next */ + 0, /* static_pass_number */ + TV_MACH_DEP, /* tv_id */ + 0, /* properties_required */ + 0, /* properties_provided */ + 0, /* properties_destroyed */ + 0, /* todo_flags_start */ + 0 /* todo_flags_finish */ + } +}; + +/* pass_delay_slots and rest_of_handle_machine_reorg_nocfg are not CFG-aware, + which means they do not properly maintain it and may even fail if the + BLOCK_FOR_INSN pointers are not cleared. + These CFG-unaware passes are grouped in pass_cfg_unaware_passes. */ -/* Machine dependent reorg pass. */ +static bool +gate_cfg_unaware_passes (void) +{ +#ifdef DELAY_SLOTS + return 1; +#else + return gate_handle_machine_reorg_nocfg (); +#endif +} + +struct rtl_opt_pass pass_cfg_unaware_passes = +{ + { + RTL_PASS, + "*cfg_unaware", /* name */ + OPTGROUP_NONE, /* optinfo_flags */ + gate_cfg_unaware_passes, /* gate */ + NULL, /* execute */ + NULL, /* sub */ + NULL, /* next */ + 0, /* static_pass_number */ + TV_NONE, /* tv_id */ + 0, /* properties_required */ + 0, /* properties_provided */ + 0, /* properties_destroyed */ + 0, /* todo_flags_start */ + 0 /* todo_flags_finish */ + } +}; + +/* CFG-aware machine dependent reorg pass. */ static bool gate_handle_machine_reorg (void) { return targetm.machine_dependent_reorg != 0; } - static unsigned int rest_of_handle_machine_reorg (void) { @@ -3903,6 +3971,7 @@ struct rtl_opt_pass pass_machine_reorg = 0, /* properties_provided */ 0, /* properties_destroyed */ 0, /* todo_flags_start */ - 0 /* todo_flags_finish */ + TODO_verify_flow /* todo_flags_finish */ } }; + Index: recog.c =================================================================== --- recog.c (revision 199028) +++ recog.c (working copy) @@ -3927,6 +3927,23 @@ gate_do_final_split (void) #endif } +static unsigned int +rest_of_handle_final_split (void) +{ + if (crtl->cfg_released) + split_all_insns_noflow (); + else + { + /* Most targets expect the CFG to be destroyed at this point, + but some keep the CFG alive all the way to the final pass. */ + split_all_insns (); +#ifdef ENABLE_CHECKING + verify_flow_info (); +#endif + } + return 0; +} + struct rtl_opt_pass pass_split_for_shorten_branches = { { @@ -3934,7 +3951,7 @@ struct rtl_opt_pass pass_split_for_short "split5", /* name */ OPTGROUP_NONE, /* optinfo_flags */ gate_do_final_split, /* gate */ - split_all_insns_noflow, /* execute */ + rest_of_handle_final_split, /* execute */ NULL, /* sub */ NULL, /* next */ 0, /* static_pass_number */ Index: sched-ebb.c =================================================================== --- sched-ebb.c (revision 199028) +++ sched-ebb.c (working copy) @@ -593,8 +593,6 @@ schedule_ebbs_init (void) haifa_sched_init (); - compute_bb_for_insn (); - /* Initialize DONT_CALC_DEPS and ebb-{start, end} markers. */ bitmap_initialize (&dont_calc_deps, 0); bitmap_clear (&dont_calc_deps); Index: config/i386/i386.c =================================================================== --- config/i386/i386.c (revision 199028) +++ config/i386/i386.c (working copy) @@ -35569,10 +35569,6 @@ ix86_pad_short_function (void) static void ix86_reorg (void) { - /* We are freeing block_for_insn in the toplev to keep compatibility - with old MDEP_REORGS that are not CFG based. Recompute it now. */ - compute_bb_for_insn (); - if (optimize && optimize_function_for_speed_p (cfun)) { if (TARGET_PAD_SHORT_FUNCTION) Index: config/alpha/alpha.c =================================================================== --- config/alpha/alpha.c (revision 199028) +++ config/alpha/alpha.c (working copy) @@ -9807,8 +9807,8 @@ alpha_canonicalize_comparison (int *code #undef TARGET_ADDRESS_COST #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0 -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG alpha_reorg #undef TARGET_PROMOTE_FUNCTION_MODE #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote Index: config/frv/frv.c =================================================================== --- config/frv/frv.c (revision 199028) +++ config/frv/frv.c (working copy) @@ -477,8 +477,8 @@ static bool frv_class_likely_spilled_p #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs #undef TARGET_SETUP_INCOMING_VARARGS #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG frv_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG frv_reorg #undef TARGET_EXPAND_BUILTIN_VA_START #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start @@ -8182,7 +8182,7 @@ frv_register_nop (rtx nop) frv_nops[frv_num_nops++] = nop; } -/* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions +/* Implement TARGET_MACHINE_DEPENDENT_REORG_NOCFG. Divide the instructions into packets and check whether we need to insert nops in order to fulfill the processor's issue requirements. Also, if the user has requested a certain alignment for a label, try to meet that alignment Index: config/s390/s390.c =================================================================== --- config/s390/s390.c (revision 199028) +++ config/s390/s390.c (working copy) @@ -11036,8 +11036,8 @@ s390_loop_unroll_adjust (unsigned nunrol #undef TARGET_MEMORY_MOVE_COST #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG s390_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG s390_reorg #undef TARGET_VALID_POINTER_MODE #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode Index: config/spu/spu.c =================================================================== --- config/spu/spu.c (revision 199028) +++ config/spu/spu.c (working copy) @@ -7240,8 +7240,8 @@ static const struct attribute_spec spu_a #undef TARGET_SETUP_INCOMING_VARARGS #define TARGET_SETUP_INCOMING_VARARGS spu_setup_incoming_varargs -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG spu_machine_dependent_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG spu_machine_dependent_reorg #undef TARGET_GIMPLIFY_VA_ARG_EXPR #define TARGET_GIMPLIFY_VA_ARG_EXPR spu_gimplify_va_arg_expr Index: config/mep/mep.c =================================================================== --- config/mep/mep.c (revision 199028) +++ config/mep/mep.c (working copy) @@ -7242,8 +7242,8 @@ mep_asm_init_sections (void) #define TARGET_RTX_COSTS mep_rtx_cost #undef TARGET_ADDRESS_COST #define TARGET_ADDRESS_COST mep_address_cost -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG mep_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG mep_reorg #undef TARGET_SETUP_INCOMING_VARARGS #define TARGET_SETUP_INCOMING_VARARGS mep_setup_incoming_varargs #undef TARGET_PASS_BY_REFERENCE Index: config/tilegx/tilegx.c =================================================================== --- config/tilegx/tilegx.c (revision 199028) +++ config/tilegx/tilegx.c (working copy) @@ -5549,8 +5549,8 @@ tilegx_file_end (void) #undef TARGET_SCHED_ADJUST_COST #define TARGET_SCHED_ADJUST_COST tilegx_sched_adjust_cost -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG tilegx_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG tilegx_reorg #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \ Index: config/sh/sh.c =================================================================== --- config/sh/sh.c (revision 199028) +++ config/sh/sh.c (working copy) @@ -490,8 +490,8 @@ static const struct attribute_spec sh_at #undef TARGET_ALLOCATE_INITIAL_VALUE #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG sh_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG sh_reorg #undef TARGET_DWARF_REGISTER_SPAN #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span Index: config/avr/avr.c =================================================================== --- config/avr/avr.c (revision 199028) +++ config/avr/avr.c (working copy) @@ -9683,7 +9683,7 @@ avr_reorg_remove_redundant_compare (rtx } -/* Implement `TARGET_MACHINE_DEPENDENT_REORG'. */ +/* Implement `TARGET_MACHINE_DEPENDENT_REORG_NOCFG'. */ /* Optimize conditional jumps. */ static void @@ -12141,8 +12141,8 @@ avr_fold_builtin (tree fndecl, int n_arg #define TARGET_RTX_COSTS avr_rtx_costs #undef TARGET_ADDRESS_COST #define TARGET_ADDRESS_COST avr_address_cost -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG avr_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG avr_reorg #undef TARGET_FUNCTION_ARG #define TARGET_FUNCTION_ARG avr_function_arg #undef TARGET_FUNCTION_ARG_ADVANCE Index: config/stormy16/stormy16.c =================================================================== --- config/stormy16/stormy16.c (revision 199028) +++ config/stormy16/stormy16.c (working copy) @@ -2664,8 +2664,8 @@ xstormy16_return_in_memory (const_tree t #undef TARGET_FUNCTION_VALUE_REGNO_P #define TARGET_FUNCTION_VALUE_REGNO_P xstormy16_function_value_regno_p -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG xstormy16_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG xstormy16_reorg #undef TARGET_PREFERRED_RELOAD_CLASS #define TARGET_PREFERRED_RELOAD_CLASS xstormy16_preferred_reload_class Index: config/mn10300/mn10300.c =================================================================== --- config/mn10300/mn10300.c (revision 199028) +++ config/mn10300/mn10300.c (working copy) @@ -3308,8 +3308,8 @@ mn10300_reorg (void) /* Initialize the GCC target structure. */ -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG mn10300_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG mn10300_reorg #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" Index: config/c6x/c6x.c =================================================================== --- config/c6x/c6x.c (revision 199028) +++ config/c6x/c6x.c (working copy) @@ -5893,9 +5893,9 @@ c6x_hwloops (void) reorg_loops (true, &c6x_doloop_hooks); } -/* Implement the TARGET_MACHINE_DEPENDENT_REORG pass. We split call insns here - into a sequence that loads the return register and performs the call, - and emit the return label. +/* Implement the TARGET_MACHINE_DEPENDENT_REORG_NOCFG pass. + We split call insns here into a sequence that loads the return + register and performs the call, and emit the return label. If scheduling after reload is requested, it happens here. */ static void @@ -6796,8 +6796,8 @@ c6x_debug_unwind_info (void) #undef TARGET_PREFERRED_RENAME_CLASS #define TARGET_PREFERRED_RENAME_CLASS c6x_preferred_rename_class -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG c6x_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG c6x_reorg #undef TARGET_ASM_FILE_START #define TARGET_ASM_FILE_START c6x_file_start Index: config/ia64/ia64.c =================================================================== --- config/ia64/ia64.c (revision 199028) +++ config/ia64/ia64.c (working copy) @@ -527,8 +527,8 @@ static const struct attribute_spec ia64_ #undef TARGET_UNSPEC_MAY_TRAP_P #define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG ia64_reorg #undef TARGET_ENCODE_SECTION_INFO #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info @@ -9637,10 +9637,6 @@ emit_predicate_relation_info (void) static void ia64_reorg (void) { - /* We are freeing block_for_insn in the toplev to keep compatibility - with old MDEP_REORGS that are not CFG based. Recompute it now. */ - compute_bb_for_insn (); - /* If optimizing, we'll have split before scheduling. */ if (optimize == 0) split_all_insns (); Index: config/picochip/picochip.c =================================================================== --- config/picochip/picochip.c (revision 199028) +++ config/picochip/picochip.c (working copy) @@ -255,8 +255,8 @@ static char picochip_get_vliw_alu_id (vo #undef TARGET_ASM_FILE_END #define TARGET_ASM_FILE_END picochip_asm_file_end -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG picochip_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG picochip_reorg #undef TARGET_ARG_PARTIAL_BYTES #define TARGET_ARG_PARTIAL_BYTES picochip_arg_partial_bytes Index: config/mcore/mcore.c =================================================================== --- config/mcore/mcore.c (revision 199028) +++ config/mcore/mcore.c (working copy) @@ -191,8 +191,8 @@ static const struct attribute_spec mcore #define TARGET_RTX_COSTS mcore_rtx_costs #undef TARGET_ADDRESS_COST #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0 -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG mcore_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG mcore_reorg #undef TARGET_PROMOTE_FUNCTION_MODE #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote Index: config/tilepro/tilepro.c =================================================================== --- config/tilepro/tilepro.c (revision 199028) +++ config/tilepro/tilepro.c (working copy) @@ -5041,8 +5041,8 @@ tilepro_file_end (void) #undef TARGET_SCHED_ADJUST_COST #define TARGET_SCHED_ADJUST_COST tilepro_sched_adjust_cost -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG tilepro_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG tilepro_reorg #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \ Index: config/arm/arm.c =================================================================== --- config/arm/arm.c (revision 199028) +++ config/arm/arm.c (working copy) @@ -434,8 +434,8 @@ static const struct attribute_spec arm_a #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \ arm_autovectorize_vector_sizes -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG arm_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG arm_reorg #undef TARGET_INIT_BUILTINS #define TARGET_INIT_BUILTINS arm_init_builtins Index: config/pa/pa.c =================================================================== --- config/pa/pa.c (revision 199028) +++ config/pa/pa.c (working copy) @@ -313,8 +313,8 @@ static size_t n_deferred_plabels = 0; #undef TARGET_ADDRESS_COST #define TARGET_ADDRESS_COST hppa_address_cost -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG pa_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG pa_reorg #undef TARGET_INIT_LIBFUNCS #define TARGET_INIT_LIBFUNCS pa_init_libfuncs Index: config/mips/mips.c =================================================================== --- config/mips/mips.c (revision 199028) +++ config/mips/mips.c (working copy) @@ -16255,7 +16255,7 @@ mips16_split_long_branches (void) while (something_changed); } -/* Implement TARGET_MACHINE_DEPENDENT_REORG. */ +/* Implement TARGET_MACHINE_DEPENDENT_REORG_NOCFG. */ static void mips_reorg (void) @@ -18619,8 +18619,8 @@ mips_expand_vec_minmax (rtx target, rtx #undef TARGET_IN_SMALL_DATA_P #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG mips_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG mips_reorg #undef TARGET_PREFERRED_RELOAD_CLASS #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class Index: config/v850/v850.c =================================================================== --- config/v850/v850.c (revision 199028) +++ config/v850/v850.c (working copy) @@ -1212,7 +1212,7 @@ Saved %d bytes (%d uses of register %s) } -/* TARGET_MACHINE_DEPENDENT_REORG. On the 850, we use it to implement +/* TARGET_MACHINE_DEPENDENT_REORG_NOCFG. On the 850, we use it to implement the -mep mode to copy heavily used pointers to ep to use the implicit addressing. */ @@ -3223,8 +3223,8 @@ v850_gen_movdi (rtx * operands) #undef TARGET_ADDRESS_COST #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0 -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG v850_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG v850_reorg #undef TARGET_SCHED_ISSUE_RATE #define TARGET_SCHED_ISSUE_RATE v850_issue_rate Index: config/h8300/h8300.c =================================================================== --- config/h8300/h8300.c (revision 199028) +++ config/h8300/h8300.c (working copy) @@ -6071,8 +6071,8 @@ h8300_trampoline_init (rtx m_tramp, tree #undef TARGET_FUNCTION_ARG_ADVANCE #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG h8300_reorg #undef TARGET_HARD_REGNO_SCRATCH_OK #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok Index: config/mmix/mmix.c =================================================================== --- config/mmix/mmix.c (revision 199028) +++ config/mmix/mmix.c (working copy) @@ -226,8 +226,8 @@ static void mmix_conditional_register_us #undef TARGET_REGISTER_MOVE_COST #define TARGET_REGISTER_MOVE_COST mmix_register_move_cost -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG mmix_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG mmix_reorg #undef TARGET_PROMOTE_FUNCTION_MODE #define TARGET_PROMOTE_FUNCTION_MODE mmix_promote_function_mode @@ -828,7 +828,7 @@ mmix_target_asm_function_end_prologue (F cfun->machine->in_prologue = 0; } -/* Implement TARGET_MACHINE_DEPENDENT_REORG. No actual rearrangements +/* Implement TARGET_MACHINE_DEPENDENT_REORG_NOCFG. No actual rearrangements done here; just virtually by calculating the highest saved stack register number used to modify the register numbers at output time. */ Index: config/bfin/bfin.c =================================================================== --- config/bfin/bfin.c (revision 199028) +++ config/bfin/bfin.c (working copy) @@ -5717,8 +5717,8 @@ bfin_conditional_register_usage (void) #undef TARGET_ASM_INTEGER #define TARGET_ASM_INTEGER bfin_assemble_integer -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG bfin_reorg +#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG +#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG bfin_reorg #undef TARGET_FUNCTION_OK_FOR_SIBCALL #define TARGET_FUNCTION_OK_FOR_SIBCALL bfin_function_ok_for_sibcall