From patchwork Thu May 16 05:34:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bharat Bhushan X-Patchwork-Id: 244222 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 8DBD22C0111 for ; Thu, 16 May 2013 15:32:24 +1000 (EST) Received: from va3outboundpool.messaging.microsoft.com (va3ehsobe001.messaging.microsoft.com [216.32.180.11]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 36CFC2C00E8 for ; Thu, 16 May 2013 15:30:26 +1000 (EST) Received: from mail177-va3-R.bigfish.com (10.7.14.245) by VA3EHSOBE009.bigfish.com (10.7.40.29) with Microsoft SMTP Server id 14.1.225.23; Thu, 16 May 2013 05:30:24 +0000 Received: from mail177-va3 (localhost [127.0.0.1]) by mail177-va3-R.bigfish.com (Postfix) with ESMTP id 4E4132C0514; Thu, 16 May 2013 05:30:24 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h1ee6h1de0h1fdah1202h1e76h1d1ah1d2ah1fc6h1082kzz8275bhz2dh2a8h668h839he5bhf0ah107ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1155h) Received: from mail177-va3 (localhost.localdomain [127.0.0.1]) by mail177-va3 (MessageSwitch) id 1368682223346002_21781; Thu, 16 May 2013 05:30:23 +0000 (UTC) Received: from VA3EHSMHS022.bigfish.com (unknown [10.7.14.240]) by mail177-va3.bigfish.com (Postfix) with ESMTP id 45A942A0061; Thu, 16 May 2013 05:30:23 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS022.bigfish.com (10.7.99.32) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 16 May 2013 05:30:23 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.2.328.11; Thu, 16 May 2013 05:30:22 +0000 Received: from freescale.com ([10.232.15.72]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with SMTP id r4G5UH5f008488; Wed, 15 May 2013 22:30:18 -0700 Received: by freescale.com (sSMTP sendmail emulation); Thu, 16 May 2013 11:04:44 +0530 From: Bharat Bhushan To: , , , , , Subject: [PATCH 2/2 v2] powerpc: restore dbcr0 on user space exit Date: Thu, 16 May 2013 11:04:32 +0530 Message-ID: <1368682472-4268-3-git-send-email-Bharat.Bhushan@freescale.com> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1368682472-4268-2-git-send-email-Bharat.Bhushan@freescale.com> References: <1368682472-4268-1-git-send-email-Bharat.Bhushan@freescale.com> <1368682472-4268-2-git-send-email-Bharat.Bhushan@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Bharat Bhushan X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" On BookE (Branch taken + Single Step) is as same as Branch Taken on BookS and in Linux we simulate BookS behavior for BookE as well. When doing so, in Branch taken handling we want to set DBCR0_IC but we update the current->thread->dbcr0 and not DBCR0. Now on 64bit the current->thread.dbcr0 (and other debug registers) is synchronized ONLY on context switch flow. But after handling Branch taken in debug exception if we return back to user space without context switch then single stepping change (DBCR0_ICMP) does not get written in h/w DBCR0 and Instruction Complete exception does not happen. This fixes using ptrace reliably on BookE-PowerPC Signed-off-by: Bharat Bhushan --- v1->v2 - Subject line was not having 2/2 arch/powerpc/kernel/asm-offsets.c | 1 + arch/powerpc/kernel/entry_64.S | 24 ++++++++++++++++++++---- 2 files changed, 21 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c index b51a97c..1e2f450 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c @@ -103,6 +103,7 @@ int main(void) #endif /* CONFIG_VSX */ #ifdef CONFIG_PPC64 DEFINE(KSP_VSID, offsetof(struct thread_struct, ksp_vsid)); + DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, dbcr0)); #else /* CONFIG_PPC64 */ DEFINE(PGDIR, offsetof(struct thread_struct, pgdir)); #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 794889b..561630d 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -614,7 +614,9 @@ _GLOBAL(ret_from_except_lite) * from the interrupt. */ #ifdef CONFIG_PPC_BOOK3E + ld r3,PACACURRENT(r13) wrteei 0 + lwz r10,(THREAD+THREAD_DBCR0)(r3) #else ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */ mtmsrd r10,1 /* Update machine state */ @@ -628,15 +630,29 @@ _GLOBAL(ret_from_except_lite) /* Check current_thread_info()->flags */ andi. r0,r4,_TIF_USER_WORK_MASK + bne 1f +#ifdef CONFIG_PPC_BOOK3E + /* + * Check to see if the dbcr0 register is set up to debug. + * Use the internal debug mode bit to do this. + */ + andis. r0,r10,DBCR0_IDM@h beq restore - - andi. r0,r4,_TIF_NEED_RESCHED - beq 1f + mfmsr r0 + rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */ + mtmsr r0 + mtspr SPRN_DBCR0,r10 + li r10, -1 + mtspr SPRN_DBSR,r10 + b restore +#endif +1: andi. r0,r4,_TIF_NEED_RESCHED + beq 2f bl .restore_interrupts SCHEDULE_USER b .ret_from_except_lite -1: bl .save_nvgprs +2: bl .save_nvgprs bl .restore_interrupts addi r3,r1,STACK_FRAME_OVERHEAD bl .do_notify_resume