Patchwork [RFC] power/mpc85xx: Add delay after enabling I2C master

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Submitter York Sun
Date May 13, 2013, 9:27 p.m.
Message ID <1368480428-23926-1-git-send-email-yorksun@freescale.com>
Download mbox | patch
Permalink /patch/243540/
State RFC
Headers show

Comments

York Sun - May 13, 2013, 9:27 p.m.
Erratum A-006037 indicates I2C controller executes the write to I2CCR only
after it sees SCL idle for 64K cycle of internal I2C controller clocks. If
during this waiting period, I2C controller is disabled (I2CCR[MEN] set to
0), then the controller could end in bad state, and hang the future access
to I2C register.

The mpc_i2c_fixup() function tries to recover the bus from a stalled state
where the 9th clock pulse wasn't generated. However, this workaround
disables and enables I2C controller without meeting waiting requirement of
this erratum.

This erratum applies to some 85xx SoCs. It is safe to apply to all of them
for mpc_i2c_fixup().

Signed-off-by: York Sun <yorksun@freescale.com>
---
I'd like to get rid of the #ifdef if mpc5121 is OK with the longer delay.

 drivers/i2c/busses/i2c-mpc.c |   11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)
Scott Wood - July 23, 2013, 12:33 a.m.
On Mon, May 13, 2013 at 02:27:08PM -0700, York Sun wrote:
> Erratum A-006037 indicates I2C controller executes the write to I2CCR only
> after it sees SCL idle for 64K cycle of internal I2C controller clocks. If
> during this waiting period, I2C controller is disabled (I2CCR[MEN] set to
> 0), then the controller could end in bad state, and hang the future access
> to I2C register.
> 
> The mpc_i2c_fixup() function tries to recover the bus from a stalled state
> where the 9th clock pulse wasn't generated. However, this workaround
> disables and enables I2C controller without meeting waiting requirement of
> this erratum.
> 
> This erratum applies to some 85xx SoCs. It is safe to apply to all of them
> for mpc_i2c_fixup().
> 
> Signed-off-by: York Sun <yorksun@freescale.com>
> 
> ---
> I'd like to get rid of the #ifdef if mpc5121 is OK with the longer delay.

Are mpc5121 and mpc85xx the only things that use this?

Are you sure the delay always works out to be longer?  What is the
relationship between fsl_get_sys_freq() and i2c->real_clk?

In any case, you should send this patch to the i2c maintainer and list.

-Scott
York Sun - July 23, 2013, 3:37 p.m.
On 07/22/2013 05:33 PM, Scott Wood wrote:
> On Mon, May 13, 2013 at 02:27:08PM -0700, York Sun wrote:
>> Erratum A-006037 indicates I2C controller executes the write to I2CCR only
>> after it sees SCL idle for 64K cycle of internal I2C controller clocks. If
>> during this waiting period, I2C controller is disabled (I2CCR[MEN] set to
>> 0), then the controller could end in bad state, and hang the future access
>> to I2C register.
>>
>> The mpc_i2c_fixup() function tries to recover the bus from a stalled state
>> where the 9th clock pulse wasn't generated. However, this workaround
>> disables and enables I2C controller without meeting waiting requirement of
>> this erratum.
>>
>> This erratum applies to some 85xx SoCs. It is safe to apply to all of them
>> for mpc_i2c_fixup().
>>
>> Signed-off-by: York Sun <yorksun@freescale.com>
>>
>> ---
>> I'd like to get rid of the #ifdef if mpc5121 is OK with the longer delay.
> 
> Are mpc5121 and mpc85xx the only things that use this?

No. 83xx and 86xx also uses this file. But I am only unsure if mpc52xx
is OK with this extended delay. I guess they are but I don't have a
proof, or someone to confirm.

> 
> Are you sure the delay always works out to be longer?  What is the
> relationship between fsl_get_sys_freq() and i2c->real_clk?

Yes. The max divider from sys clock to i2c clcok is 32K. i2c->real_clk
is the clock I2C controller pumps out, not its internal operation clock.

> 
> In any case, you should send this patch to the i2c maintainer and list.
> 

I don't have the name on top of my head. Is that linux-i2c@vger.kernel.org?

York

Patch

diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index a69459e..3e540ca 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -105,7 +105,12 @@  static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
 {
 	int k;
-	u32 delay_val = 1000000 / i2c->real_clk + 1;
+	u32 delay_val;
+#ifdef CONFIG_PPC_85xx
+	delay_val = 65536 / (fsl_get_sys_freq() / 2000000);	/* 64K cycle */
+#else
+	delay_val = 1000000 / i2c->real_clk + 1;
+#endif
 
 	if (delay_val < 2)
 		delay_val = 2;
@@ -115,7 +120,11 @@  static void mpc_i2c_fixup(struct mpc_i2c *i2c)
 		writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
 		udelay(delay_val);
 		writeccr(i2c, CCR_MEN);
+#ifdef CONFIG_PPC_85xx
+		udelay(delay_val);
+#else
 		udelay(delay_val << 1);
+#endif
 	}
 }