From patchwork Mon May 13 15:14:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petar Jovanovic X-Patchwork-Id: 243424 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3B8B12C0091 for ; Tue, 14 May 2013 01:18:09 +1000 (EST) Received: from localhost ([::1]:37490 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UbuVr-0003TY-Cj for incoming@patchwork.ozlabs.org; Mon, 13 May 2013 11:18:07 -0400 Received: from eggs.gnu.org ([208.118.235.92]:44184) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UbuVc-0003TT-49 for qemu-devel@nongnu.org; Mon, 13 May 2013 11:17:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UbuVa-0006tX-TD for qemu-devel@nongnu.org; Mon, 13 May 2013 11:17:52 -0400 Received: from mail.rt-rk.ftn.uns.ac.rs ([147.91.177.140]:45180 helo=mail.rt-rk.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UbuVa-0006tD-MW for qemu-devel@nongnu.org; Mon, 13 May 2013 11:17:50 -0400 Received: from mail.rt-rk.com (mail.localdomain [127.0.0.1]) by mail.rt-rk.com (Postfix) with SMTP id A581725B322 for ; Mon, 13 May 2013 17:17:47 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Petar Jovanovic To: qemu-devel@nongnu.org Date: Mon, 13 May 2013 17:14:35 +0200 Message-Id: <1368458075-18819-1-git-send-email-petar.jovanovic@rt-rk.com> X-Mailer: git-send-email 1.7.9.5 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 147.91.177.140 Cc: petar.jovanovic@imgtec.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH] target-mips: set carry bit correctly in DSPControl register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Petar Jovanovic First we need to clear the bit and then we set the given value. Instruction ADDSC sets the bit and instruction ADDWC uses this bit. Signed-off-by: Petar Jovanovic --- target-mips/dsp_helper.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 9212789..e98bac8 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -53,9 +53,10 @@ static inline void set_DSPControl_overflow_flag(uint32_t flag, int position, env->active_tc.DSPControl |= (target_ulong)flag << position; } -static inline void set_DSPControl_carryflag(uint32_t flag, CPUMIPSState *env) +static inline void set_DSPControl_carryflag(bool flag, CPUMIPSState *env) { - env->active_tc.DSPControl |= (target_ulong)flag << 13; + env->active_tc.DSPControl &= ~(1 << 13); + env->active_tc.DSPControl |= flag << 13; } static inline uint32_t get_DSPControl_carryflag(CPUMIPSState *env) @@ -1266,7 +1267,7 @@ SUBUH_QB(subuh_r, 1); target_ulong helper_addsc(target_ulong rs, target_ulong rt, CPUMIPSState *env) { uint64_t temp, tempRs, tempRt; - int32_t flag; + bool flag; tempRs = (uint64_t)rs & MIPSDSP_LLO; tempRt = (uint64_t)rt & MIPSDSP_LLO;