From patchwork Mon May 13 01:35:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petar Jovanovic X-Patchwork-Id: 243231 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 355F72C00A9 for ; Mon, 13 May 2013 11:39:14 +1000 (EST) Received: from localhost ([::1]:59438 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UbhjM-0004zl-3Q for incoming@patchwork.ozlabs.org; Sun, 12 May 2013 21:39:12 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48830) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ubhj7-0004zf-E2 for qemu-devel@nongnu.org; Sun, 12 May 2013 21:38:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ubhj6-0000ns-DE for qemu-devel@nongnu.org; Sun, 12 May 2013 21:38:57 -0400 Received: from mail.rt-rk.ftn.uns.ac.rs ([147.91.177.140]:58437 helo=mail.rt-rk.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ubhj6-0000ni-2W for qemu-devel@nongnu.org; Sun, 12 May 2013 21:38:56 -0400 Received: from mail.rt-rk.com (mail.localdomain [127.0.0.1]) by mail.rt-rk.com (Postfix) with SMTP id B73BE25BD77 for ; Mon, 13 May 2013 03:38:52 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Petar Jovanovic To: qemu-devel@nongnu.org Date: Mon, 13 May 2013 03:35:37 +0200 Message-Id: <1368408937-114555-1-git-send-email-petar.jovanovic@rt-rk.com> X-Mailer: git-send-email 1.7.9.5 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 147.91.177.140 Cc: peter.maydell@linaro.org, petar.jovanovic@imgtec.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v2] target-mips: clean-up in BIT_INSV X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Petar Jovanovic This is a small follow-up change to "fix incorrect behaviour for INSV". It includes two minor modifications: - sizefilter is constant so it can be moved inside of the block, - several lines of the code are replaced with a call to deposit64. No functional change. Signed-off-by: Petar Jovanovic --- v2: - version one was based on Aurelien comments, - version two includes update (use of deposit64 helper) per Peter Maydell's suggestion. target-mips/dsp_helper.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 9212789..af2aa05 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -19,6 +19,7 @@ #include "cpu.h" #include "helper.h" +#include "qemu/bitops.h" /* As the byte ordering doesn't matter, i.e. all columns are treated identically, these unions can be used directly. */ @@ -2900,13 +2901,13 @@ target_ulong helper_bitrev(target_ulong rt) return (target_ulong)rd; } -#define BIT_INSV(name, posfilter, sizefilter, ret_type) \ +#define BIT_INSV(name, posfilter, ret_type) \ target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \ target_ulong rt) \ { \ uint32_t pos, size, msb, lsb; \ - target_ulong filter; \ - target_ulong temp, temprs, temprt; \ + uint32_t const sizefilter = 0x3F; \ + target_ulong temp; \ target_ulong dspc; \ \ dspc = env->active_tc.DSPControl; \ @@ -2921,18 +2922,14 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \ return rt; \ } \ \ - filter = ((int64_t)0x01 << size) - 1; \ - filter = filter << pos; \ - temprs = (rs << pos) & filter; \ - temprt = rt & ~filter; \ - temp = temprs | temprt; \ + temp = deposit64(rt, pos, size, rs); \ \ return (target_long)(ret_type)temp; \ } -BIT_INSV(insv, 0x1F, 0x3F, int32_t); +BIT_INSV(insv, 0x1F, int32_t); #ifdef TARGET_MIPS64 -BIT_INSV(dinsv, 0x7F, 0x3F, target_long); +BIT_INSV(dinsv, 0x7F, target_long); #endif #undef BIT_INSV