powerpc: Add support for CoreInt delivery of interrupts onMPIC

Submitted by Dave Liu on March 11, 2009, 2:20 p.m.

Details

Message ID D7CCA83BB0796C49BC0BB53B6AB12089136E4B@zch01exm21.fsl.freescale.net
State Not Applicable, archived
Headers show

Commit Message

Dave Liu March 11, 2009, 2:20 p.m.
according to the latest UM, the MPIC_GREG_GCONF_COREINT should be
0x60000000.

Comments

Benjamin Herrenschmidt March 20, 2009, 5:40 a.m.
On Wed, 2009-03-11 at 22:20 +0800, Liu Dave-R63238 wrote:
> --- a/arch/powerpc/include/asm/mpic.h
> +++ b/arch/powerpc/include/asm/mpic.h
> @@ -22,6 +22,7 @@
>  #define MPIC_GREG_FEATURE_1            0x00010
>  #define MPIC_GREG_GLOBAL_CONF_0                0x00020
>  #define                MPIC_GREG_GCONF_RESET
> 0x80000000
> +#define                MPIC_GREG_GCONF_COREINT
> 0x40000000
>  #define                MPIC_GREG_GCONF_8259_PTHROU_DIS
> 0x20000000
>  #define                MPIC_GREG_GCONF_NO_BIAS
> 0x10000000
>  #define                MPIC_GREG_GCONF_BASE_MASK
> 0x000fffff
> 
> 
> according to the latest UM, the MPIC_GREG_GCONF_COREINT should be
> 0x60000000.
> 
You mean 0x40000000 ? :-)

0x60000000 looks indeed bogus.

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--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -22,6 +22,7 @@ 
 #define MPIC_GREG_FEATURE_1		0x00010
 #define MPIC_GREG_GLOBAL_CONF_0		0x00020
 #define		MPIC_GREG_GCONF_RESET			0x80000000
+#define		MPIC_GREG_GCONF_COREINT			0x40000000
 #define		MPIC_GREG_GCONF_8259_PTHROU_DIS		0x20000000
 #define		MPIC_GREG_GCONF_NO_BIAS			0x10000000
 #define		MPIC_GREG_GCONF_BASE_MASK		0x000fffff