Patchwork [v2] powerpc: Add support for CoreInt delivery of interrupts on MPIC

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Submitter Kumar Gala
Date March 11, 2009, 3:18 p.m.
Message ID <1236784730-616-1-git-send-email-galak@kernel.crashing.org>
Download mbox | patch
Permalink /patch/24306/
State Superseded
Delegated to: Benjamin Herrenschmidt
Headers show

Comments

Kumar Gala - March 11, 2009, 3:18 p.m.
CoreInt provides a mechansim to deliver the IRQ vector directly
into the core on an interrupt (via the SPR EPR) rather than having
to go IACK on the PIC.  This is suppose to provide an improvment
in interrupt latency by reducing the time to get the IRQ vector.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
* Fixed MPIC_GREG_GCONF_COREINT flag to be 0x60000000 as per spec and pointed about by Dave

 arch/powerpc/include/asm/mpic.h |    5 +++++
 arch/powerpc/sysdev/mpic.c      |   30 ++++++++++++++++++++++++++++++
 2 files changed, 35 insertions(+), 0 deletions(-)
Benjamin Herrenschmidt - March 20, 2009, 5:48 a.m.
On Wed, 2009-03-11 at 10:18 -0500, Kumar Gala wrote:
> CoreInt provides a mechansim to deliver the IRQ vector directly
> into the core on an interrupt (via the SPR EPR) rather than having
> to go IACK on the PIC.  This is suppose to provide an improvment
> in interrupt latency by reducing the time to get the IRQ vector.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> * Fixed MPIC_GREG_GCONF_COREINT flag to be 0x60000000 as per spec and pointed about by Dave

Are you sure ? That's 2 bits ...

Ben.
Kumar Gala - March 20, 2009, 11:47 a.m.
On Mar 20, 2009, at 12:48 AM, Benjamin Herrenschmidt wrote:

> On Wed, 2009-03-11 at 10:18 -0500, Kumar Gala wrote:
>> CoreInt provides a mechansim to deliver the IRQ vector directly
>> into the core on an interrupt (via the SPR EPR) rather than having
>> to go IACK on the PIC.  This is suppose to provide an improvment
>> in interrupt latency by reducing the time to get the IRQ vector.
>>
>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
>> ---
>> * Fixed MPIC_GREG_GCONF_COREINT flag to be 0x60000000 as per spec  
>> and pointed about by Dave
>
> Are you sure ? That's 2 bits ...

Yeah.  We expanded the mode field to two bits (mask would be 0x60000000)

0x00 = pass through (interrupts routed to IRQ0)
0x01 = Mixed mode
0x10 = reserved
0x11 = External proxy / coreint

- k
Benjamin Herrenschmidt - March 20, 2009, 10:08 p.m.
On Fri, 2009-03-20 at 06:47 -0500, Kumar Gala wrote:
> On Mar 20, 2009, at 12:48 AM, Benjamin Herrenschmidt wrote:
> 
> > On Wed, 2009-03-11 at 10:18 -0500, Kumar Gala wrote:
> >> CoreInt provides a mechansim to deliver the IRQ vector directly
> >> into the core on an interrupt (via the SPR EPR) rather than having
> >> to go IACK on the PIC.  This is suppose to provide an improvment
> >> in interrupt latency by reducing the time to get the IRQ vector.
> >>
> >> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> >> ---
> >> * Fixed MPIC_GREG_GCONF_COREINT flag to be 0x60000000 as per spec  
> >> and pointed about by Dave
> >
> > Are you sure ? That's 2 bits ...
> 
> Yeah.  We expanded the mode field to two bits (mask would be 0x60000000)
> 
> 0x00 = pass through (interrupts routed to IRQ0)
> 0x01 = Mixed mode
> 0x10 = reserved
> 0x11 = External proxy / coreint

Ah ok, that's a bit funny but should do. Maybe worth a comment though.

Cheers,
Ben.

Patch

diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c2ccca5..475b06e 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -22,6 +22,7 @@ 
 #define MPIC_GREG_FEATURE_1		0x00010
 #define MPIC_GREG_GLOBAL_CONF_0		0x00020
 #define		MPIC_GREG_GCONF_RESET			0x80000000
+#define		MPIC_GREG_GCONF_COREINT			0x60000000
 #define		MPIC_GREG_GCONF_8259_PTHROU_DIS		0x20000000
 #define		MPIC_GREG_GCONF_NO_BIAS			0x10000000
 #define		MPIC_GREG_GCONF_BASE_MASK		0x000fffff
@@ -357,6 +358,8 @@  struct mpic
 #define MPIC_BROKEN_FRR_NIRQS		0x00000800
 /* Destination only supports a single CPU at a time */
 #define MPIC_SINGLE_DEST_CPU		0x00001000
+/* Enable CoreInt delivery of interrupts */
+#define MPIC_ENABLE_COREINT		0x00002000
 
 /* MPIC HW modification ID */
 #define MPIC_REGSET_MASK		0xf0000000
@@ -470,6 +473,8 @@  extern void mpic_end_irq(unsigned int irq);
 extern unsigned int mpic_get_one_irq(struct mpic *mpic);
 /* This one gets from the primary mpic */
 extern unsigned int mpic_get_irq(void);
+/* This one gets from the primary mpic via CoreInt*/
+extern unsigned int mpic_get_coreint_irq(void);
 /* Fetch Machine Check interrupt from primary mpic */
 extern unsigned int mpic_get_mcirq(void);
 
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index a35297d..6fca4f1 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1169,6 +1169,12 @@  struct mpic * __init mpic_alloc(struct device_node *node,
 			mb();
 	}
 
+	/* CoreInt */
+	if (flags & MPIC_ENABLE_COREINT)
+		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
+			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
+			   | MPIC_GREG_GCONF_COREINT);
+
 	if (flags & MPIC_ENABLE_MCK)
 		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
 			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
@@ -1524,6 +1530,30 @@  unsigned int mpic_get_irq(void)
 	return mpic_get_one_irq(mpic);
 }
 
+unsigned int mpic_get_coreint_irq(void)
+{
+	struct mpic *mpic = mpic_primary;
+	u32 src;
+
+	BUG_ON(mpic == NULL);
+
+	src = mfspr(SPRN_EPR);
+
+	if (unlikely(src == mpic->spurious_vec)) {
+		if (mpic->flags & MPIC_SPV_EOI)
+			mpic_eoi(mpic);
+		return NO_IRQ;
+	}
+	if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
+		if (printk_ratelimit())
+			printk(KERN_WARNING "%s: Got protected source %d !\n",
+			       mpic->name, (int)src);
+		return NO_IRQ;
+	}
+
+	return irq_linear_revmap(mpic->irqhost, src);
+}
+
 unsigned int mpic_get_mcirq(void)
 {
 	struct mpic *mpic = mpic_primary;