Patchwork [for,1.5] target-i386 ROR r8/r16 imm instruction fix

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Submitter Aurelien Jarno
Date May 9, 2013, 5:40 p.m.
Message ID <1368121227-10885-1-git-send-email-aurelien@aurel32.net>
Download mbox | patch
Permalink /patch/242803/
State New
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Comments

Aurelien Jarno - May 9, 2013, 5:40 p.m.
Fix EFLAGS corruption by ROR r8/r16 imm instruction located at the end
of the TB, similarly to commit 089305ac for the non-immediate case.

Reported-by: Hervé Poussineau <hpoussin@reactos.org>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-i386/translate.c |    1 +
 1 file changed, 1 insertion(+)
Richard Henderson - May 9, 2013, 5:41 p.m.
On 05/09/2013 10:40 AM, Aurelien Jarno wrote:
> Fix EFLAGS corruption by ROR r8/r16 imm instruction located at the end
> of the TB, similarly to commit 089305ac for the non-immediate case.
> 
> Reported-by: Hervé Poussineau <hpoussin@reactos.org>
> Cc: Richard Henderson <rth@twiddle.net>
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> ---
>  target-i386/translate.c |    1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~

Patch

diff --git a/target-i386/translate.c b/target-i386/translate.c
index 524a0b4..0aeccdb 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -1871,6 +1871,7 @@  static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
         if (is_right) {
             tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask - 1);
             tcg_gen_shri_tl(cpu_cc_dst, cpu_T[0], mask);
+            tcg_gen_andi_tl(cpu_cc_dst, cpu_cc_dst, 1);
         } else {
             tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask);
             tcg_gen_andi_tl(cpu_cc_dst, cpu_T[0], 1);