From patchwork Wed May 8 09:17:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minghuan Lian X-Patchwork-Id: 242733 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 737292C0358 for ; Thu, 9 May 2013 19:17:38 +1000 (EST) Received: from co1outboundpool.messaging.microsoft.com (co1ehsobe006.messaging.microsoft.com [216.32.180.189]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id D2BC42C00DC for ; Thu, 9 May 2013 19:17:11 +1000 (EST) Received: from mail144-co1-R.bigfish.com (10.243.78.225) by CO1EHSOBE016.bigfish.com (10.243.66.79) with Microsoft SMTP Server id 14.1.225.23; Thu, 9 May 2013 09:17:05 +0000 Received: from mail144-co1 (localhost [127.0.0.1]) by mail144-co1-R.bigfish.com (Postfix) with ESMTP id D2A6ECA01CF for ; Thu, 9 May 2013 09:17:05 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h1ee6h1de0h1fdah1202h1e76h1d1ah1d2ah1fc6hzz8275bhz2dh2a8h668h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1155h) Received: from mail144-co1 (localhost.localdomain [127.0.0.1]) by mail144-co1 (MessageSwitch) id 1368091024683870_15274; Thu, 9 May 2013 09:17:04 +0000 (UTC) Received: from CO1EHSMHS029.bigfish.com (unknown [10.243.78.250]) by mail144-co1.bigfish.com (Postfix) with ESMTP id A5153C8004A for ; Thu, 9 May 2013 09:17:04 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO1EHSMHS029.bigfish.com (10.243.66.39) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 9 May 2013 09:17:04 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.2.328.11; Thu, 9 May 2013 09:17:03 +0000 Received: from lmh.ap.freescale.net (lmh.ap.freescale.net [10.193.20.24]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r499H0mk012090; Thu, 9 May 2013 02:17:02 -0700 From: Minghuan Lian To: Subject: [PATCH] powerpc/fsl: add property 'reg' to pcie@0 node Date: Wed, 8 May 2013 17:17:21 +0800 Message-ID: <1368004641-12405-1-git-send-email-Minghuan.Lian@freescale.com> X-Mailer: git-send-email 1.8.1.2 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Minghuan Lian , Zang Roy-R61911 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The property 'reg' is used to identify the PCIe device. if there is no 'reg' the PCI driver can not find PCI device node corresponding to PCI controller, and can not map the interrupts. So all the INTx interrupts can not be used. Signed-off-by: Minghuan Lian --- arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 1 + arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi index 7399154..d82c8da 100644 --- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi @@ -49,6 +49,7 @@ interrupts = <20 2 0 0>; fsl,iommu-parent = <&pamu0>; pcie@0 { + reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi index bd611a9..3a6179f 100644 --- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi @@ -48,6 +48,7 @@ bus-range = <0x0 0xff>; interrupts = <20 2 0 0>; pcie@0 { + reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; @@ -74,6 +75,7 @@ bus-range = <0 0xff>; interrupts = <21 2 0 0>; pcie@0 { + reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; @@ -100,6 +102,7 @@ bus-range = <0x0 0xff>; interrupts = <22 2 0 0>; pcie@0 { + reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; @@ -126,6 +129,7 @@ bus-range = <0x0 0xff>; interrupts = <23 2 0 0>; pcie@0 { + reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>;