Patchwork [U-Boot,5/6] am335x_evm:Add support for the NOR module on the memory cape

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Submitter Tom Rini
Date May 8, 2013, 10:45 p.m.
Message ID <1368053157-28317-5-git-send-email-trini@ti.com>
Download mbox | patch
Permalink /patch/242658/
State Superseded
Delegated to: Tom Rini
Headers show

Comments

Tom Rini - May 8, 2013, 10:45 p.m.
From: Steve Kipisz <s-kipisz2@ti.com>

This patch adds support for the NOR module that attaches
to the memory cape for a Beaglebone board. This does not
add booting support; only support so that you can boot from
SD/MMC and see the NOR module so that it can be programmed.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
[trini: Clean up config changes slightly]
Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/mem.c        |   30 +++++++++++++++++-
 arch/arm/include/asm/arch-am33xx/mem.h |    9 ++++++
 board/ti/am335x/mux.c                  |   53 ++++++++++++++++++++++++++++++++
 boards.cfg                             |    1 +
 include/configs/am335x_evm.h           |   28 +++++++++++++++++
 5 files changed, 120 insertions(+), 1 deletion(-)
Peter Korsgaard - May 12, 2013, 9:19 p.m.
>>>>> "Tom" == Tom Rini <trini@ti.com> writes:

Space missing after ':' in subject.

 Tom> From: Steve Kipisz <s-kipisz2@ti.com>
 Tom> This patch adds support for the NOR module that attaches
 Tom> to the memory cape for a Beaglebone board. This does not
 Tom> add booting support; only support so that you can boot from
 Tom> SD/MMC and see the NOR module so that it can be programmed.

 Tom> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
 Tom> [trini: Clean up config changes slightly]
 Tom> Signed-off-by: Tom Rini <trini@ti.com>
 Tom> ---
 Tom>  arch/arm/cpu/armv7/am33xx/mem.c        |   30 +++++++++++++++++-
 Tom>  arch/arm/include/asm/arch-am33xx/mem.h |    9 ++++++
 Tom>  board/ti/am335x/mux.c                  |   53 ++++++++++++++++++++++++++++++++
 Tom>  boards.cfg                             |    1 +
 Tom>  include/configs/am335x_evm.h           |   28 +++++++++++++++++
 Tom>  5 files changed, 120 insertions(+), 1 deletion(-)

 Tom> diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c
 Tom> index b86b0de..e46201a 100644
 Tom> --- a/arch/arm/cpu/armv7/am33xx/mem.c
 Tom> +++ b/arch/arm/cpu/armv7/am33xx/mem.c
 Tom> @@ -46,6 +46,19 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
 Tom>  };
 Tom>  #endif
 
 Tom> +#if defined(CONFIG_CMD_FLASH)
 Tom> +static const u32 gpmc_nor[GPMC_MAX_REG] = {
 Tom> +	STNOR_GPMC_CONFIG1,
 Tom> +	STNOR_GPMC_CONFIG2,
 Tom> +	STNOR_GPMC_CONFIG3,
 Tom> +	STNOR_GPMC_CONFIG4,
 Tom> +	STNOR_GPMC_CONFIG5,
 Tom> +	STNOR_GPMC_CONFIG6,
 Tom> +	STNOR_GPMC_CONFIG7
 Tom> +};

These values (and the gmpc_m_nand ones) are platform specific, right? It
would be nicer to have them in the board file than here, similar to how
I did for the ddr settings some time ago.


 Tom> +
 Tom> +#define GPMC_CS 0
 Tom> +#endif
 
 Tom>  void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 Tom>  			u32 size)
 Tom> @@ -75,16 +88,22 @@ void gpmc_init(void)
 Tom>  	/* putting a blanket check on GPMC based on ZeBu for now */
 Tom>  	gpmc_cfg = (struct gpmc *)GPMC_BASE;
 
 Tom> -#ifdef CONFIG_CMD_NAND
 Tom> +#if defined(CONFIG_CMD_NAND) || defined(CONFIG_NOR)
 Tom>  	const u32 *gpmc_config = NULL;
 Tom>  	u32 base = 0;
 Tom>  	u32 size = 0;
 Tom>  #endif
 Tom>  	/* global settings */
 Tom>  	writel(0x00000008, &gpmc_cfg->sysconfig);
 Tom> +#ifdef CONFIG_NOR
 Tom> +	writel(0x00000000, &gpmc_cfg->irqstatus);
 Tom> +	writel(0x00000000, &gpmc_cfg->irqenable);
 Tom> +	writel(0x00000A00, &gpmc_cfg->config);
 Tom> +#else
 Tom>  	writel(0x00000100, &gpmc_cfg->irqstatus);
 Tom>  	writel(0x00000100, &gpmc_cfg->irqenable);
 Tom>  	writel(0x00000012, &gpmc_cfg->config);
 Tom> +#endif

So now you cannot E.G. have a single binary working on both the nand
flash of the evm and beaglebone? That's not really nice.
Tom Rini - May 13, 2013, 1:31 p.m.
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Hash: SHA1

On 05/12/2013 05:19 PM, Peter Korsgaard wrote:
>>>>>> "Tom" == Tom Rini <trini@ti.com> writes:
> 
> Space missing after ':' in subject.

Whoops.

> Tom> From: Steve Kipisz <s-kipisz2@ti.com> Tom> This patch adds 
> support for the NOR module that attaches Tom> to the memory cape 
> for a Beaglebone board. This does not Tom> add booting support; 
> only support so that you can boot from Tom> SD/MMC and see the NOR 
> module so that it can be programmed.
> 
> Tom> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Tom> [trini: 
> Clean up config changes slightly] Tom> Signed-off-by: Tom Rini 
> <trini@ti.com> Tom> --- Tom>  arch/arm/cpu/armv7/am33xx/mem.c |
> 30 +++++++++++++++++- Tom> arch/arm/include/asm/arch-am33xx/mem.h |
> 9 ++++++ Tom> board/ti/am335x/mux.c                  |   53 
> ++++++++++++++++++++++++++++++++ Tom>  boards.cfg |    1 + Tom>
> include/configs/am335x_evm.h           |   28 +++++++++++++++++
> Tom>  5 files changed, 120 insertions(+), 1 deletion(-)
> 
> Tom> diff --git a/arch/arm/cpu/armv7/am33xx/mem.c 
> b/arch/arm/cpu/armv7/am33xx/mem.c Tom> index b86b0de..e46201a 
> 100644 Tom> --- a/arch/arm/cpu/armv7/am33xx/mem.c Tom> +++ 
> b/arch/arm/cpu/armv7/am33xx/mem.c Tom> @@ -46,6 +46,19 @@ static 
> const u32 gpmc_m_nand[GPMC_MAX_REG] = { Tom>  }; Tom>  #endif
> 
> Tom> +#if defined(CONFIG_CMD_FLASH) Tom> +static const u32 
> gpmc_nor[GPMC_MAX_REG] = { Tom> +	STNOR_GPMC_CONFIG1, Tom> + 
> STNOR_GPMC_CONFIG2, Tom> +	STNOR_GPMC_CONFIG3, Tom> + 
> STNOR_GPMC_CONFIG4, Tom> +	STNOR_GPMC_CONFIG5, Tom> + 
> STNOR_GPMC_CONFIG6, Tom> +	STNOR_GPMC_CONFIG7 Tom> +};
> 
> These values (and the gmpc_m_nand ones) are platform specific, 
> right? It would be nicer to have them in the board file than here, 
> similar to how I did for the ddr settings some time ago.

The GPMC setup stuff has historically been, lets say less than
optimal.  We might be able to move this to board_init like omap3 does,
however.  I'll check.

> Tom> + Tom> +#define GPMC_CS 0 Tom> +#endif
> 
> Tom>  void enable_gpmc_cs_config(const u32 *gpmc_config, struct 
> gpmc_cs *cs, u32 base, Tom>  			u32 size) Tom> @@ -75,16 +88,22 @@ 
> void gpmc_init(void) Tom>  	/* putting a blanket check on GPMC 
> based on ZeBu for now */ Tom>  	gpmc_cfg = (struct gpmc 
> *)GPMC_BASE;
> 
> Tom> -#ifdef CONFIG_CMD_NAND Tom> +#if defined(CONFIG_CMD_NAND) || 
> defined(CONFIG_NOR) Tom>  	const u32 *gpmc_config = NULL; Tom> u32
> base = 0; Tom>  	u32 size = 0; Tom>  #endif Tom>  	/* global 
> settings */ Tom>  	writel(0x00000008, &gpmc_cfg->sysconfig); Tom> 
> +#ifdef CONFIG_NOR Tom> +	writel(0x00000000, &gpmc_cfg->irqstatus);
> Tom> +	writel(0x00000000, &gpmc_cfg->irqenable); Tom> +
> writel(0x00000A00, &gpmc_cfg->config); Tom> +#else Tom>
> writel(0x00000100, &gpmc_cfg->irqstatus); Tom>
> writel(0x00000100, &gpmc_cfg->irqenable); Tom>
> writel(0x00000012, &gpmc_cfg->config); Tom> +#endif
> 
> So now you cannot E.G. have a single binary working on both the 
> nand flash of the evm and beaglebone? That's not really nice.

It's worse than that.  We don't have a NOR cape, we have a memory cape
and NOR module.  We could have a memory cape and NAND module.  And
there's not a nice way at run-time to determine if we've got one or
the other.

- -- 
Tom
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Patch

diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c
index b86b0de..e46201a 100644
--- a/arch/arm/cpu/armv7/am33xx/mem.c
+++ b/arch/arm/cpu/armv7/am33xx/mem.c
@@ -46,6 +46,19 @@  static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
 };
 #endif
 
+#if defined(CONFIG_CMD_FLASH)
+static const u32 gpmc_nor[GPMC_MAX_REG] = {
+	STNOR_GPMC_CONFIG1,
+	STNOR_GPMC_CONFIG2,
+	STNOR_GPMC_CONFIG3,
+	STNOR_GPMC_CONFIG4,
+	STNOR_GPMC_CONFIG5,
+	STNOR_GPMC_CONFIG6,
+	STNOR_GPMC_CONFIG7
+};
+
+#define GPMC_CS 0
+#endif
 
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size)
@@ -75,16 +88,22 @@  void gpmc_init(void)
 	/* putting a blanket check on GPMC based on ZeBu for now */
 	gpmc_cfg = (struct gpmc *)GPMC_BASE;
 
-#ifdef CONFIG_CMD_NAND
+#if defined(CONFIG_CMD_NAND) || defined(CONFIG_NOR)
 	const u32 *gpmc_config = NULL;
 	u32 base = 0;
 	u32 size = 0;
 #endif
 	/* global settings */
 	writel(0x00000008, &gpmc_cfg->sysconfig);
+#ifdef CONFIG_NOR
+	writel(0x00000000, &gpmc_cfg->irqstatus);
+	writel(0x00000000, &gpmc_cfg->irqenable);
+	writel(0x00000A00, &gpmc_cfg->config);
+#else
 	writel(0x00000100, &gpmc_cfg->irqstatus);
 	writel(0x00000100, &gpmc_cfg->irqenable);
 	writel(0x00000012, &gpmc_cfg->config);
+#endif
 	/*
 	 * Disable the GPMC0 config set by ROM code
 	 */
@@ -98,4 +117,13 @@  void gpmc_init(void)
 	size = PISMO1_NAND_SIZE;
 	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
 #endif
+
+#ifdef CONFIG_NOR
+	/* NOR - CS0 */
+	gpmc_config = gpmc_nor;
+	base = CONFIG_SYS_FLASH_BASE;
+	size = GPMC_SIZE_16M;
+	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
+	writel(0x00000a00, 0x50000050);
+#endif
 }
diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h
index c3bf74e..ddcad62 100644
--- a/arch/arm/include/asm/arch-am33xx/mem.h
+++ b/arch/arm/include/asm/arch-am33xx/mem.h
@@ -61,6 +61,15 @@ 
 #define M_NAND_GPMC_CONFIG6	0x16000f80
 #define M_NAND_GPMC_CONFIG7	0x00000008
 
+/* NOR chip on NOR module for Beaglebone */
+#define STNOR_GPMC_CONFIG1	0x00001200
+#define STNOR_GPMC_CONFIG2	0x00101000
+#define STNOR_GPMC_CONFIG3	0x00030301
+#define STNOR_GPMC_CONFIG4	0x10041004
+#define STNOR_GPMC_CONFIG5	0x000C1010
+#define STNOR_GPMC_CONFIG6	0x08070280
+#define STNOR_GPMC_CONFIG7	0x00000F48
+
 /* max number of GPMC Chip Selects */
 #define GPMC_MAX_CS		8
 /* max number of GPMC regs */
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 2e09d98..187468e 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -190,6 +190,56 @@  static struct module_pin_mux nand_pin_mux[] = {
 	{-1},
 };
 
+#if defined(CONFIG_NOR)
+static struct module_pin_mux bone_norcape_pin_mux[] = {
+	{OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A0 */
+	{OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A1 */
+	{OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A2 */
+	{OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A3 */
+	{OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A4 */
+	{OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A5 */
+	{OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A6 */
+	{OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A7 */
+	{OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A8 */
+	{OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A9 */
+	{OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE},       /* NOR_A10 */
+	{OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */
+	{OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A12 */
+	{OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A13 */
+	{OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A14 */
+	{OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A15 */
+	{OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A16 */
+	{OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A17 */
+	{OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A18 */
+	{OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A19 */
+	{OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD0 */
+	{OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD1 */
+	{OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD2 */
+	{OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD3 */
+	{OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD4 */
+	{OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD5 */
+	{OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD6 */
+	{OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD7 */
+	{OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD8 */
+	{OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD9 */
+	{OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD10 */
+	{OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD11 */
+	{OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD12 */
+	{OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD13 */
+	{OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD14 */
+	{OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD15 */
+
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE},   /* NOR_CE */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)},    /* NOR_WEN */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */
+	{-1},
+};
+#endif
+
+
 void enable_uart0_pin_mux(void)
 {
 	configure_module_pin_mux(uart0_pin_mux);
@@ -268,6 +318,9 @@  void enable_board_pin_mux(struct am335x_baseboard_id *header)
 		configure_module_pin_mux(mii1_pin_mux);
 		configure_module_pin_mux(mmc0_pin_mux);
 		configure_module_pin_mux(mmc1_pin_mux);
+#if defined(CONFIG_NOR)
+		configure_module_pin_mux(bone_norcape_pin_mux);
+#endif
 	} else if (board_is_gp_evm(header)) {
 		/* General Purpose EVM */
 		unsigned short profile = detect_daughter_board_profile();
diff --git a/boards.cfg b/boards.cfg
index 5d78064..d74840d 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -236,6 +236,7 @@  integratorap_cm946es         arm         arm946es    integrator          armltd
 integratorcp_cm946es         arm         arm946es    integrator          armltd         -               integratorcp:CM946ES
 ca9x4_ct_vxp                 arm         armv7       vexpress            armltd
 am335x_evm                   arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1
+am335x_evm_nor               arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,NOR
 am335x_evm_spiboot           arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT
 am335x_evm_uart1             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL2,CONS_INDEX=2
 am335x_evm_uart2             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL3,CONS_INDEX=3
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 90cc1f5..343a4aa 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -496,4 +496,32 @@ 
 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
 #endif
 
+/*
+ * NOR Size = 16 MiB
+ * Number of Sectors/Blocks = 128
+ * Sector Size = 128 KiB
+ * Word length = 16 bits
+ * Default layout:
+ * 0x000000 - 0x07FFFF : U-Boot (512 KiB)
+ * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB)
+ * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB)
+ * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB)
+ * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
+ */
+#if defined(CONFIG_NOR)
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BASE		(0x08000000)
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_FLASH
+#endif  /* NOR support */
+
 #endif	/* ! __CONFIG_AM335X_EVM_H */