[U-Boot,3/6] am335x_evm: Only set CONFIG_NAND when !CONFIG_SPI_BOOT

Due to hardware design, we can't have NAND present (as we know of NAND
today) when booting from SPI, so disable NAND then as that simplifies
logic.

Signed-off-by: Tom Rini <trini@ti.com>
---
 include/configs/am335x_evm.h |    9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

>>>>> "Tom" == Tom Rini <trini@ti.com> writes:

 Tom> Due to hardware design, we can't have NAND present (as we know of NAND
 Tom> today) when booting from SPI, so disable NAND then as that simplifies
 Tom> logic.

Sorry, this description is not clear to me. I didn't check in detail,
but as far as I remember the default pins for spi0 don't conflict with
gmpc.

It's also not quite clear to me if you refer to SW support for NAND
flash or the hardware component when you say 'NAND' above.


 Tom> Signed-off-by: Tom Rini <trini@ti.com>
 Tom> ---
 Tom>  include/configs/am335x_evm.h |    9 +++++++--
 Tom>  1 file changed, 7 insertions(+), 2 deletions(-)

 Tom> diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
 Tom> index 004a06a..90cc1f5 100644
 Tom> --- a/include/configs/am335x_evm.h
 Tom> +++ b/include/configs/am335x_evm.h
 Tom> @@ -230,7 +230,9 @@
 Tom>  /* USB Device Firmware Update support */
 Tom>  #define CONFIG_DFU_FUNCTION
 Tom>  #define CONFIG_DFU_MMC
 Tom> +#ifdef CONFIG_NAND
 Tom>  #define CONFIG_DFU_NAND
 Tom> +#endif
 Tom>  #define CONFIG_CMD_DFU
 Tom>  #define DFU_ALT_INFO_MMC \
 Tom>  	"boot part 0 1;" \
 Tom> @@ -335,6 +337,7 @@
 Tom>  #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
 
 Tom>  #define CONFIG_SPL_BOARD_INIT
 Tom> +#ifdef CONFIG_NAND
 Tom>  #define CONFIG_SPL_NAND_AM33XX_BCH
 Tom>  #define CONFIG_SPL_NAND_SUPPORT
 Tom>  #define CONFIG_SPL_NAND_BASE
 Tom> @@ -365,6 +368,7 @@
 Tom>  #define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 
 Tom>  #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 Tom> +#endif
 
 Tom>  /*
 Tom>   * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 Tom> @@ -466,7 +470,10 @@
 Tom>  #define CONFIG_PHY_ADDR			0
 Tom>  #define CONFIG_PHY_SMSC
 
 Tom> +#if !defined(CONFIG_SPI_BOOT)
 Tom>  #define CONFIG_NAND
 Tom> +#endif
 Tom> +
 Tom>  /* NAND support */
 Tom>  #ifdef CONFIG_NAND
 Tom>  #define CONFIG_CMD_NAND
 Tom> @@ -484,11 +491,9 @@
 Tom>  							/* CS0 */
 Tom>  #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND
 Tom>  							   devices */
 Tom> -#if !defined(CONFIG_SPI_BOOT)
 Tom>  #define CONFIG_ENV_IS_IN_NAND
 Tom>  #define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
 Tom>  #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
 Tom>  #endif
 Tom> -#endif
 
 Tom>  #endif	/* ! __CONFIG_AM335X_EVM_H */
 Tom> -- 
 Tom> 1.7.9.5

 Tom> _______________________________________________
 Tom> U-Boot mailing list
 Tom> U-Boot@lists.denx.de
 Tom> http://lists.denx.de/mailman/listinfo/u-boot

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On 05/12/2013 05:08 PM, Peter Korsgaard wrote:
>>>>>> "Tom" == Tom Rini <trini@ti.com> writes:
> 
> Tom> Due to hardware design, we can't have NAND present (as we know
> of NAND Tom> today) when booting from SPI, so disable NAND then as
> that simplifies Tom> logic.
> 
> Sorry, this description is not clear to me. I didn't check in
> detail, but as far as I remember the default pins for spi0 don't
> conflict with gmpc.
> 
> It's also not quite clear to me if you refer to SW support fo
> NAND flash or the hardware component when you say 'NAND' above.

OK, good point.  I'm talking about HW support, and it should be
spelled put better.  Note that we're talking about the TI GP EVM, EVM
SK, BeagleBone White and BeagleBone Black here, and not custom
hardware.  The EVM SK does not allow for expansion such as adding
NAND/NOR flash and probably not SPI.  The GP EVM can have only one of
NOR, NAND or SPI flash active based on the profile that is selected
for the whole hardware stack.  The BeagleBone White may have a "memory
cape" installed which in turn can have a NAND, NOR or eMMC board
plugged into it.  It's not impossible someone could come up with a SPI
flash cape and plug the memory cape into that, or come up with a
complex breadboard solution.  But lets see that happen and work before
worrying about that particular permutation.

- -- 
Tom
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

iQIcBAEBAgAGBQJRkNrAAAoJENk4IS6UOR1W2lEQALB95Qfrrc1iE0QkccAOPC+q
ODZLj9UQd6emu/Fs+jQjyEhkiBr63EjTf7N1yy03ixz45NIsibgAzf8hTJ7pOEjG
tbbqyHOUx7ATkApO5olhHqFYLtvUyhvAG3Tqg9adnXVWv0xggO3zXEw2e7x/yhPt
TC2uDmnVZeQxAmSmJ6V0RxUmoZYegRL6HeQAO4xM20YekWZxj+JQ08Cuyk8/hmwI
as5Fww713Qx2cDTkzGvut5wsd3ilGrIkkV9RIbooTP3gVX23ZUuyGfB/1E4DaRIn
bOwofKDWefOPssbNWoNf7moHaDRgvr//H5mH6P7ItUpym0bJjD/TArIeriueojF2
pNoi0czRRuYnWbgVbbzJdpbsp+O7acm8dEmNUoULMqvdyhFH1ZC1QMRwrohK26wT
6AP/JrWZq5xWzxeCzMf2YWzgZNN7dJgiFvVzCGAFTO7RLehKFgkTtT18eYfr6Tlr
NOueiIMJC01nwYv5iyIyyDRZsEERix2YIjt1K1B++X3r8lbhXUCuWac63mpeVryR
QjB/K+jNTojhwk5i9e6GSxdJYlRA8Rcv8AprQyHXL8QC19iNwsKww/yqCfFW/nkR
C75qRom6B/m5uxPyurdTwJnxjda1PNsB9HXZ6zuUUsHRy7rB+1XjGLRL7bhPheKN
uaQcsJPkFJUfaVINpdyY
=2mnd
-----END PGP SIGNATURE-----