Patchwork arm/zynq: Add software reset

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Submitter Sebastian Huber
Date May 8, 2013, 12:55 p.m.
Message ID <1368017724-21851-1-git-send-email-sebastian.huber@embedded-brains.de>
Download mbox | patch
Permalink /patch/242579/
State New
Headers show

Comments

Sebastian Huber - May 8, 2013, 12:55 p.m.
---
 hw/misc/zynq_slcr.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)
Peter Crosthwaite - May 13, 2013, 11:49 p.m.
Hi Sebastian,

Thanks for your contribution,

On Wed, May 8, 2013 at 10:55 PM, Sebastian Huber
<sebastian.huber@embedded-brains.de> wrote:
> ---
>  hw/misc/zynq_slcr.c |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
> index 8418327..e88702e 100644
> --- a/hw/misc/zynq_slcr.c
> +++ b/hw/misc/zynq_slcr.c
> @@ -396,6 +396,9 @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
>                  goto bad_reg;
>              }
>              s->reset[(offset - 0x200) / 4] = val;
> +            if (offset == 0x200 && val == 0x1) {

The reset will only work if you have all the write-ignore bits in val
cleared. Bit 0 is independent of those. It should read:

            if (offset == 0x200 && val & 0x1) {

To mask off all the don't care bits.

Regards,
Peter

> +                qemu_system_reset_request();
> +            }
>              break;
>          case 0x300:
>              s->apu_ctrl = val;
> --
> 1.7.7
>
>
Peter Crosthwaite - June 7, 2013, 4:19 a.m.
Hi Sebastian,

I'd like to get this merged with the fix I suggested. Are you able to
remake or ok if I ammend and resend your patch?

Regards,
Peter

On Tue, May 14, 2013 at 9:49 AM, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> Hi Sebastian,
>
> Thanks for your contribution,
>
> On Wed, May 8, 2013 at 10:55 PM, Sebastian Huber
> <sebastian.huber@embedded-brains.de> wrote:
>> ---
>>  hw/misc/zynq_slcr.c |    3 +++
>>  1 files changed, 3 insertions(+), 0 deletions(-)
>>
>> diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
>> index 8418327..e88702e 100644
>> --- a/hw/misc/zynq_slcr.c
>> +++ b/hw/misc/zynq_slcr.c
>> @@ -396,6 +396,9 @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
>>                  goto bad_reg;
>>              }
>>              s->reset[(offset - 0x200) / 4] = val;
>> +            if (offset == 0x200 && val == 0x1) {
>
> The reset will only work if you have all the write-ignore bits in val
> cleared. Bit 0 is independent of those. It should read:
>
>             if (offset == 0x200 && val & 0x1) {
>
> To mask off all the don't care bits.
>
> Regards,
> Peter
>
>> +                qemu_system_reset_request();
>> +            }
>>              break;
>>          case 0x300:
>>              s->apu_ctrl = val;
>> --
>> 1.7.7
>>
>>
Sebastian Huber - June 7, 2013, 8:22 a.m.
On 06/07/2013 06:19 AM, Peter Crosthwaite wrote:
> Hi Sebastian,
>
> I'd like to get this merged with the fix I suggested. Are you able to
> remake or ok if I ammend and resend your patch?

I am fine with your change.  My version is to restrictive.

Patch

diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
index 8418327..e88702e 100644
--- a/hw/misc/zynq_slcr.c
+++ b/hw/misc/zynq_slcr.c
@@ -396,6 +396,9 @@  static void zynq_slcr_write(void *opaque, hwaddr offset,
                 goto bad_reg;
             }
             s->reset[(offset - 0x200) / 4] = val;
+            if (offset == 0x200 && val == 0x1) {
+                qemu_system_reset_request();
+            }
             break;
         case 0x300:
             s->apu_ctrl = val;