From patchwork Wed May 8 09:57:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Bolton X-Patchwork-Id: 242537 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 058C02C00DE for ; Wed, 8 May 2013 19:58:13 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=aelDS2QlPS35mWN0rv2JOCkKIeXF3YpfIOsQfh6N6mJtn/CjVt6lS +uWfHZZEj2xnld5FxOhOw5iA3Tb+z12NOlPieGpl3Bspm5hi7kXAOt+dMdcuDb2y ZYrca3yTOAOOWJqBIiJJKb35/WpfSuchnnl+MGyqZ8PPurIlaPELPk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=pUZ52A+YBhbCjKbRYFGcCTGHmLg=; b=k/NnBQLnNgV0hyC/pLxr jsZHMOHFLQY1h6n0S7iP3e65IT88JorWnkOm7d152+mJUJZh2DL82/Pem3tjrmoJ eqmefYouiucCJ/+cS4Y69MobosTNQY85WbYqfZU/BX3/7VlcDsyYyHuMmA9WCy2Z N9GBuGiO8fv/6Mgdk5qAvBQ= Received: (qmail 7787 invoked by alias); 8 May 2013 09:58:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 7774 invoked by uid 89); 8 May 2013 09:58:07 -0000 X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, MSGID_MULTIPLE_AT, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=no version=3.3.1 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Wed, 08 May 2013 09:57:38 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Wed, 08 May 2013 10:57:35 +0100 Received: from E102352xp ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 8 May 2013 10:57:34 +0100 From: "Ian Bolton" To: Subject: [PATCH, AArch64] Support BFI instruction and insv standard pattern Date: Wed, 8 May 2013 10:57:21 +0100 Message-ID: <000101ce4bd2$6f17d010$4d477030$@bolton@arm.com> MIME-Version: 1.0 X-MC-Unique: 113050810573505001 X-Virus-Found: No Hi, This patch implements the BFI variant of BFM. In doing so, it also implements the insv standard pattern. I've regression tested on bare-metal and linux. It comes complete with its own compilation and execution testcase. OK for trunk? Cheers, Ian 2013-05-08 Ian Bolton gcc/ * config/aarch64/aarch64.md (insv): New define_expand. (*insv_reg): New define_insn. testsuite/ * gcc.target/aarch64/bfm_1.c: New test. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 330f78c..b730ed0 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3118,6 +3118,53 @@ (set_attr "mode" "")] ) +;; Bitfield Insert (insv) +(define_expand "insv" + [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand") + (match_operand 1 "const_int_operand") + (match_operand 2 "const_int_operand")) + (match_operand:GPI 3 "general_operand"))] + "" +{ + HOST_WIDE_INT mask = ((HOST_WIDE_INT)1 << INTVAL (operands[1])) - 1; + + if (GET_MODE_BITSIZE (mode) > BITS_PER_WORD + || INTVAL (operands[1]) < 1 + || INTVAL (operands[1]) >= GET_MODE_BITSIZE (mode) + || INTVAL (operands[2]) < 0 + || (INTVAL (operands[2]) + INTVAL (operands[1])) + > GET_MODE_BITSIZE (mode)) + FAIL; + + /* Prefer AND/OR for inserting all zeros or all ones. */ + if (CONST_INT_P (operands[3]) + && ((INTVAL (operands[3]) & mask) == 0 + || (INTVAL (operands[3]) & mask) == mask)) + FAIL; + + if (!register_operand (operands[3], mode)) + operands[3] = force_reg (mode, operands[3]); + + /* Intentional fall-through, which will lead to below pattern + being matched. */ +}) + +(define_insn "*insv_reg" + [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r") + (match_operand 1 "const_int_operand" "n") + (match_operand 2 "const_int_operand" "n")) + (match_operand:GPI 3 "register_operand" "r"))] + "!(GET_MODE_BITSIZE (mode) > BITS_PER_WORD + || INTVAL (operands[1]) < 1 + || INTVAL (operands[1]) >= GET_MODE_BITSIZE (mode) + || INTVAL (operands[2]) < 0 + || (INTVAL (operands[2]) + INTVAL (operands[1])) + > GET_MODE_BITSIZE (mode))" + "bfi\\t%0, %3, %2, %1" + [(set_attr "v8type" "bfm") + (set_attr "mode" "")] +) + (define_insn "*_shft_" [(set (match_operand:GPI 0 "register_operand" "=r") (ashift:GPI (ANY_EXTEND:GPI diff --git a/gcc/testsuite/gcc.target/aarch64/bfm_1.c b/gcc/testsuite/gcc.target/aarch64/bfm_1.c new file mode 100644 index 0000000..d9a73a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/bfm_1.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps -fno-inline" } */ + +extern void abort (void); + +typedef struct bitfield +{ + unsigned short eight: 8; + unsigned short four: 4; + unsigned short five: 5; + unsigned short seven: 7; +} bitfield; + +bitfield +bfi1 (bitfield a) +{ + /* { dg-final { scan-assembler "bfi\tw\[0-9\]+, w\[0-9\]+, 0, 8" } } */ + a.eight = 3; + return a; +} + +bitfield +bfi2 (bitfield a) +{ + /* { dg-final { scan-assembler "bfi\tw\[0-9\]+, w\[0-9\]+, 16, 5" } } */ + a.five = 7; + return a; +} + +int +main (int argc, char** argv) +{ + bitfield a; + bitfield b = bfi1 (a); + bitfield c = bfi2 (b); + + if (c.eight != 3) + abort (); + + if (c.five != 7) + abort (); + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */