From patchwork Tue May 7 19:30:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torbjorn Granlund X-Patchwork-Id: 242434 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3103C2C00F3 for ; Wed, 8 May 2013 05:31:02 +1000 (EST) Received: from localhost ([::1]:58703 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UZnbI-0006H4-6C for incoming@patchwork.ozlabs.org; Tue, 07 May 2013 15:31:00 -0400 Received: from eggs.gnu.org ([208.118.235.92]:47501) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UZnan-0006GY-QZ for qemu-devel@nongnu.org; Tue, 07 May 2013 15:30:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UZnak-0005f8-VU for qemu-devel@nongnu.org; Tue, 07 May 2013 15:30:29 -0400 Received: from gmplib-02.nada.kth.se ([130.237.222.242]:38323 helo=shell.gmplib.org) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UZnak-0005ep-O9; Tue, 07 May 2013 15:30:26 -0400 Received: by shell.gmplib.org (Postfix, from userid 1001) id 9B7191209D; Tue, 7 May 2013 21:30:24 +0200 (CEST) To: Alexander Graf , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson References: <86sj20rql4.fsf@shell.gmplib.org> <5187ECAD.4050901@suse.de> <86obcorn76.fsf@shell.gmplib.org> <15FCEEAE-FE2D-44B9-9DC3-5419B29D5B16@suse.de> <86a9o7qe3u.fsf_-_@shell.gmplib.org> <86fvxypyru.fsf_-_@shell.gmplib.org> <518935E4.70908@suse.de> <8638typsnp.fsf@shell.gmplib.org> From: Torbjorn Granlund Date: Tue, 07 May 2013 21:30:24 +0200 In-Reply-To: <8638typsnp.fsf@shell.gmplib.org> (Torbjorn Granlund's message of "Tue\, 07 May 2013 20\:10\:50 +0200") Message-ID: <86ppx2oaen.fsf@shell.gmplib.org> User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.3 (berkeley-unix) MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 8.x X-Received-From: 130.237.222.242 Subject: Re: [Qemu-devel] [Qemu-ppc] Incorrect handling of more PPC64 insns (PATCH) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org I realised a possible problem with my suggested patch. What about a 32-bit processor? Then NARROW_MODE macro is identical 0. The pre-patch behaviour was then to ignore the L bit and decode both 32-bit and 64-bit instruction in the same way. Apparently that is correct behaviour. (The manual is slightly vague, but I let hardware decide.) With my patch, the bit is not ignored, and invalid code will be generated for 32-bit targets, if they'd set the L bit. Here is an uglier but hopefully completely correct patch. diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 1a84653..69d684c 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -675,49 +675,65 @@ static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) /* cmp */ static void gen_cmp(DisasContext *ctx) { - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { +#if defined(TARGET_PPC64) + if (!(ctx->opcode & 0x00200000)) { +#endif gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1, crfD(ctx->opcode)); +#if defined(TARGET_PPC64) } else { gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1, crfD(ctx->opcode)); } +#endif } /* cmpi */ static void gen_cmpi(DisasContext *ctx) { - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { +#if defined(TARGET_PPC64) + if (!(ctx->opcode & 0x00200000)) { +#endif gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1, crfD(ctx->opcode)); +#if defined(TARGET_PPC64) } else { gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1, crfD(ctx->opcode)); } +#endif } /* cmpl */ static void gen_cmpl(DisasContext *ctx) { - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { +#if defined(TARGET_PPC64) + if (!(ctx->opcode & 0x00200000)) { +#endif gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 0, crfD(ctx->opcode)); +#if defined(TARGET_PPC64) } else { gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 0, crfD(ctx->opcode)); } +#endif } /* cmpli */ static void gen_cmpli(DisasContext *ctx) { - if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) { +#if defined(TARGET_PPC64) + if (!(ctx->opcode & 0x00200000)) { +#endif gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 0, crfD(ctx->opcode)); +#if defined(TARGET_PPC64) } else { gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 0, crfD(ctx->opcode)); } +#endif } /* isel (PowerPC 2.03 specification) */