@@ -29,6 +29,7 @@ COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
COBJS-$(CONFIG_DW_I2C) += designware_i2c.o
COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
+COBJS-$(CONFIG_FTI2C010) += fti2c010.o
COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
new file mode 100644
@@ -0,0 +1,371 @@
+/*
+ * Faraday I2C Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+#include "fti2c010.h"
+
+#define I2C_RD 1
+#define I2C_WR 0
+
+#define CFG_I2C_TIMEOUT CONFIG_SYS_HZ
+
+struct fti2c010_chip {
+ void __iomem *regs;
+ uint32_t bus;
+ uint32_t speed;
+};
+
+#if defined(CONFIG_HARD_I2C)
+
+static struct fti2c010_chip chip_list[] = {
+#ifdef CONFIG_I2C_MULTI_BUS
+# ifdef CONFIG_FTI2C010_BASE
+ {
+ .bus = 0,
+ .speed = 0,
+ .regs = (void __iomem *)CONFIG_FTI2C010_BASE,
+ },
+# endif
+# ifdef CONFIG_FTI2C010_BASE1
+ {
+ .bus = 1,
+ .speed = 0,
+ .regs = (void __iomem *)CONFIG_FTI2C010_BASE1,
+ },
+# endif
+# ifdef CONFIG_FTI2C010_BASE2
+ {
+ .bus = 2,
+ .speed = 0,
+ .regs = (void __iomem *)CONFIG_FTI2C010_BASE2,
+ },
+# endif
+# ifdef CONFIG_FTI2C010_BASE3
+ {
+ .bus = 3,
+ .speed = 0,
+ .regs = (void __iomem *)CONFIG_FTI2C010_BASE3,
+ },
+# endif
+#else /* #ifdef CONFIG_I2C_MULTI_BUS */
+ {
+ .bus = 0,
+ .speed = 0,
+ .regs = (void __iomem *)CONFIG_FTI2C010_BASE,
+ },
+#endif /* #ifdef CONFIG_I2C_MULTI_BUS */
+};
+
+static struct fti2c010_chip *priv = chip_list;
+
+static int fti2c010_wait(uint32_t mask)
+{
+ int ret = -1;
+ uint32_t stat, ts;
+ struct fti2c010_regs __iomem *regs = priv->regs;
+
+ for (ts = get_timer(0); get_timer(ts) < CFG_I2C_TIMEOUT; ) {
+ stat = readl(®s->sr);
+ if ((stat & mask) == mask) {
+ ret = 0;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/*
+ * u-boot I2C API
+ */
+
+/*
+ * Initialization, must be called once on start up, may be called
+ * repeatedly to change the speed and slave addresses.
+ */
+void i2c_init(int speed, int slaveaddr)
+{
+ if (speed || priv->speed == 0)
+ i2c_set_bus_speed(speed);
+}
+
+/*
+ * Probe the given I2C chip address. Returns 0 if a chip responded,
+ * not 0 on failure.
+ */
+int i2c_probe(uchar chip)
+{
+ int rc;
+ struct fti2c010_regs __iomem *regs = priv->regs;
+
+ i2c_init(0, chip);
+
+ /* 1. Select slave device (7bits Address + 1bit R/W) */
+ writel((chip << 1) + I2C_WR, ®s->dr);
+ writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
+ rc = fti2c010_wait(SR_DT);
+ if (rc)
+ return rc;
+
+ /* 2. Select device register */
+ writel(0, ®s->dr);
+ writel(CR_ENABLE | CR_TBEN, ®s->cr);
+ rc = fti2c010_wait(SR_DT);
+
+ return rc;
+}
+
+/*
+ * Read/Write interface:
+ * chip: I2C chip address, range 0..127
+ * addr: Memory (register) address within the chip
+ * alen: Number of bytes to use for addr (typically 1, 2 for larger
+ * memories, 0 for register type devices with only one
+ * register)
+ * buffer: Where to read/write the data
+ * len: How many bytes to read/write
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+ int rc, pos;
+ uchar paddr[4];
+ struct fti2c010_regs __iomem *regs = priv->regs;
+
+ i2c_init(0, chip);
+
+ paddr[0] = (addr >> 0) & 0xFF;
+ paddr[1] = (addr >> 8) & 0xFF;
+ paddr[2] = (addr >> 16) & 0xFF;
+ paddr[3] = (addr >> 24) & 0xFF;
+
+ /*
+ * Phase A. Set register address
+ */
+
+ /* A.1 Select slave device (7bits Address + 1bit R/W) */
+ writel((chip << 1) + I2C_WR, ®s->dr);
+ writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
+ rc = fti2c010_wait(SR_DT);
+ if (rc)
+ return rc;
+
+ /* A.2 Select device register */
+ for (pos = 0; pos < alen; ++pos) {
+ uint32_t ctrl = CR_ENABLE | CR_TBEN;
+
+ writel(paddr[pos], ®s->dr);
+ writel(ctrl, ®s->cr);
+ rc = fti2c010_wait(SR_DT);
+ if (rc)
+ return rc;
+ }
+
+ /*
+ * Phase B. Get register data
+ */
+
+ /* B.1 Select slave device (7bits Address + 1bit R/W) */
+ writel((chip << 1) + I2C_RD, ®s->dr);
+ writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
+ rc = fti2c010_wait(SR_DT);
+ if (rc)
+ return rc;
+
+ /* B.2 Get register data */
+ for (pos = 0; pos < len; ++pos) {
+ uint32_t ctrl = CR_ENABLE | CR_TBEN;
+ uint32_t stat = SR_DR;
+
+ if (pos == len - 1) {
+ ctrl |= CR_NAK | CR_STOP;
+ stat |= SR_ACK;
+ }
+ writel(ctrl, ®s->cr);
+ rc = fti2c010_wait(stat);
+ if (rc)
+ break;
+ buf[pos] = (uchar)(readl(®s->dr) & 0xFF);
+ }
+
+ return rc;
+}
+
+/*
+ * Read/Write interface:
+ * chip: I2C chip address, range 0..127
+ * addr: Memory (register) address within the chip
+ * alen: Number of bytes to use for addr (typically 1, 2 for larger
+ * memories, 0 for register type devices with only one
+ * register)
+ * buffer: Where to read/write the data
+ * len: How many bytes to read/write
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+ int rc, pos;
+ uchar paddr[4];
+ struct fti2c010_regs __iomem *regs = priv->regs;
+
+ i2c_init(0, chip);
+
+ paddr[0] = (addr >> 0) & 0xFF;
+ paddr[1] = (addr >> 8) & 0xFF;
+ paddr[2] = (addr >> 16) & 0xFF;
+ paddr[3] = (addr >> 24) & 0xFF;
+
+ /*
+ * Phase A. Set register address
+ */
+
+ /* A.1 Select slave device (7bits Address + 1bit R/W) */
+ writel((chip << 1) + I2C_WR, ®s->dr);
+ writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
+ rc = fti2c010_wait(SR_DT);
+ if (rc)
+ return rc;
+
+ /* A.2 Select device register */
+ for (pos = 0; pos < alen; ++pos) {
+ uint32_t ctrl = CR_ENABLE | CR_TBEN;
+
+ writel(paddr[pos], ®s->dr);
+ writel(ctrl, ®s->cr);
+ rc = fti2c010_wait(SR_DT);
+ if (rc)
+ return rc;
+ }
+
+ /*
+ * Phase B. Set register data
+ */
+
+ for (pos = 0; pos < len; ++pos) {
+ uint32_t ctrl = CR_ENABLE | CR_TBEN;
+
+ if (pos == len - 1)
+ ctrl |= CR_STOP;
+ writel(buf[pos], ®s->dr);
+ writel(ctrl, ®s->cr);
+ rc = fti2c010_wait(SR_DT);
+ if (rc)
+ break;
+ }
+
+ return rc;
+}
+
+/*
+ * Functions for setting the current I2C bus and its speed
+ */
+#ifdef CONFIG_I2C_MULTI_BUS
+
+/*
+ * i2c_set_bus_num:
+ *
+ * Change the active I2C bus. Subsequent read/write calls will
+ * go to this one.
+ *
+ * bus - bus index, zero based
+ *
+ * Returns: 0 on success, not 0 on failure
+ *
+ */
+int i2c_set_bus_num(unsigned int bus)
+{
+ if (bus >= sizeof(chip_list) / sizeof(chip_list[0]))
+ return -1;
+ priv = chip_list + bus;
+ i2c_init(5000, 0);
+ return 0;
+}
+
+/*
+ * i2c_get_bus_num:
+ *
+ * Returns index of currently active I2C bus. Zero-based.
+ */
+
+unsigned int i2c_get_bus_num(void)
+{
+ return priv->bus;
+}
+
+#endif /* #ifdef CONFIG_I2C_MULTI_BUS */
+
+/*
+ * i2c_set_bus_speed:
+ *
+ * Change the speed of the active I2C bus
+ *
+ * speed - bus speed in Hz
+ *
+ * Returns: 0 on success, not 0 on failure
+ *
+ */
+int i2c_set_bus_speed(unsigned int speed)
+{
+ struct fti2c010_regs __iomem *regs = priv->regs;
+#ifdef CONFIG_FTI2C010_SCLK
+ ulong apb = CONFIG_FTI2C010_SCLK;
+#else
+ ulong apb = clk_get_rate("I2C");
+#endif
+ ulong div = 0x640;
+ ulong gsr = 0;
+ ulong tsr = 0x20;
+ ulong ts;
+
+ writel(CR_I2CRST, ®s->cr);
+ for (ts = get_timer(0); get_timer(ts) < CFG_I2C_TIMEOUT; ) {
+ if (readl(®s->cr) & CR_I2CRST)
+ continue;
+ break;
+ }
+ if (readl(®s->cr) & CR_I2CRST) {
+ printf("fti2c010: reset timeout\n");
+ return -1;
+ }
+
+ /* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
+ priv->speed = apb / (2 * (div + 2) + gsr);
+
+ if (speed > 0) {
+ for (div = 0; div < 0x3ffff; ++div) {
+ priv->speed = apb / (2 * (div + 2) + gsr);
+ if (priv->speed < speed)
+ break;
+ }
+ }
+
+ writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), ®s->tgsr);
+ writel(CDR_DIV(div), ®s->cdr);
+
+ return 0;
+}
+
+/*
+ * i2c_get_bus_speed:
+ *
+ * Returns speed of currently active I2C bus in Hz
+ */
+
+unsigned int i2c_get_bus_speed(void)
+{
+ return priv->speed;
+}
+
+#endif /* CONFIG_HARD_I2C */
new file mode 100644
@@ -0,0 +1,81 @@
+/*
+ * Faraday I2C Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#ifndef __FTI2C010_H
+#define __FTI2C010_H
+
+/*
+ * FTI2C010 registers
+ */
+struct fti2c010_regs {
+ uint32_t cr; /* 0x00: control register */
+ uint32_t sr; /* 0x04: status register */
+ uint32_t cdr; /* 0x08: clock division register */
+ uint32_t dr; /* 0x0c: data register */
+ uint32_t sar; /* 0x10: slave address register */
+ uint32_t tgsr;/* 0x14: time & glitch suppression register */
+ uint32_t bmr; /* 0x18: bus monitor register */
+ uint32_t rsvd[5];
+ uint32_t revr;/* 0x30: revision register */
+};
+
+/*
+ * control register
+ */
+#define CR_ALIRQ 0x2000 /* arbitration lost interrupt (master) */
+#define CR_SAMIRQ 0x1000 /* slave address match interrupt (slave) */
+#define CR_STOPIRQ 0x800 /* stop condition interrupt (slave) */
+#define CR_NAKRIRQ 0x400 /* NACK response interrupt (master) */
+#define CR_DRIRQ 0x200 /* rx interrupt (both) */
+#define CR_DTIRQ 0x100 /* tx interrupt (both) */
+#define CR_TBEN 0x80 /* tx enable (both) */
+#define CR_NAK 0x40 /* NACK (both) */
+#define CR_STOP 0x20 /* stop (master) */
+#define CR_START 0x10 /* start (master) */
+#define CR_GCEN 0x8 /* general call support (slave) */
+#define CR_SCLEN 0x4 /* enable clock out (master) */
+#define CR_I2CEN 0x2 /* enable I2C (both) */
+#define CR_I2CRST 0x1 /* reset I2C (both) */
+#define CR_ENABLE \
+ (CR_ALIRQ | CR_NAKRIRQ | CR_DRIRQ | CR_DTIRQ | CR_SCLEN | CR_I2CEN)
+
+/*
+ * status register
+ */
+#define SR_CLRAL 0x400 /* clear arbitration lost */
+#define SR_CLRGC 0x200 /* clear general call */
+#define SR_CLRSAM 0x100 /* clear slave address match */
+#define SR_CLRSTOP 0x80 /* clear stop */
+#define SR_CLRNAKR 0x40 /* clear NACK respond */
+#define SR_DR 0x20 /* rx ready */
+#define SR_DT 0x10 /* tx done */
+#define SR_BB 0x8 /* bus busy */
+#define SR_BUSY 0x4 /* chip busy */
+#define SR_ACK 0x2 /* ACK/NACK received */
+#define SR_RW 0x1 /* set when master-rx or slave-tx mode */
+
+/*
+ * clock division register
+ */
+#define CDR_DIV(n) ((n) & 0x3ffff)
+
+/*
+ * time & glitch suppression register
+ */
+#define TGSR_GSR(n) (((n) & 0x7) << 10)
+#define TGSR_TSR(n) ((n) & 0x3ff)
+
+/*
+ * bus monitor register
+ */
+#define BMR_SCL 0x2 /* SCL is pull-up */
+#define BMR_SDA 0x1 /* SDA is pull-up */
+
+#endif /* __FTI2C010_H */