From patchwork Tue May 7 05:49:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar Kushwaha X-Patchwork-Id: 241980 X-Patchwork-Delegate: afleming@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 9AE212C0124 for ; Tue, 7 May 2013 15:50:35 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 45C664A208; Tue, 7 May 2013 07:50:32 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MFP1jVV8TrL6; Tue, 7 May 2013 07:50:31 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CF7B34A1F2; Tue, 7 May 2013 07:50:25 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5E1354A1F2 for ; Tue, 7 May 2013 07:50:19 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WERzqp9GhCRV for ; Tue, 7 May 2013 07:50:14 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe005.messaging.microsoft.com [216.32.181.185]) by theia.denx.de (Postfix) with ESMTPS id 373364A1F1 for ; Tue, 7 May 2013 07:50:07 +0200 (CEST) Received: from mail221-ch1-R.bigfish.com (10.43.68.250) by CH1EHSOBE016.bigfish.com (10.43.70.66) with Microsoft SMTP Server id 14.1.225.23; Tue, 7 May 2013 05:50:06 +0000 Received: from mail221-ch1 (localhost [127.0.0.1]) by mail221-ch1-R.bigfish.com (Postfix) with ESMTP id DBD88404A8; Tue, 7 May 2013 05:50:05 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h1fc6h1ee6h1de0h1fdah1202h1e76h1d1ah1d2ahzz17326ah8275bh8275dhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1155h) Received: from mail221-ch1 (localhost.localdomain [127.0.0.1]) by mail221-ch1 (MessageSwitch) id 1367905804178540_31466; Tue, 7 May 2013 05:50:04 +0000 (UTC) Received: from CH1EHSMHS039.bigfish.com (snatpool3.int.messaging.microsoft.com [10.43.68.225]) by mail221-ch1.bigfish.com (Postfix) with ESMTP id 1FA2732006B; Tue, 7 May 2013 05:50:04 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS039.bigfish.com (10.43.69.248) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 7 May 2013 05:50:04 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.328.11; Tue, 7 May 2013 05:50:03 +0000 Received: from b32579-VirtualBox.ap.freescale.net (B32579-02.ap.freescale.net [10.232.132.191]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r475nu6M017586; Mon, 6 May 2013 22:50:01 -0700 From: Prabhakar Kushwaha To: Date: Tue, 7 May 2013 11:19:55 +0530 Message-ID: <1367905795-9005-1-git-send-email-prabhakar@freescale.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: scottwood@freescale.com, afleming@gmail.com Subject: [U-Boot] [PATCH] powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de e500v2 processor does not support 8K page size TLB entries. So create new TLB entry only during NAND SPL boot. Signed-off-by: Prabhakar Kushwaha --- Based upon git://git.denx.de/u-boot.git branch master This patch depends upon following patch set 1) powerpc/mpc85xx:No NOR boot, do not compile IFC errata A003399 http://patchwork.ozlabs.org/patch/236849/ 2) powerpc/mpc85xx: new SPL support for IFC NAND http://patchwork.ozlabs.org/patch/236850/ 3) board/p1010rdb:Add NAND boot support using new SPL format http://patchwork.ozlabs.org/patch/236851/ 4) board/bsc9131rdb:Add NAND boot support using new SPL format http://patchwork.ozlabs.org/patch/236852/ 5) board/bsc9132qds:Add NAND boot support using new SPL format http://patchwork.ozlabs.org/patch/236853/ board/freescale/bsc9131rdb/tlb.c | 11 ++++++++--- board/freescale/bsc9132qds/tlb.c | 11 ++++++++--- board/freescale/p1010rdb/tlb.c | 7 ++++++- 3 files changed, 22 insertions(+), 7 deletions(-) diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c index 243a38f..f65868f 100644 --- a/board/freescale/bsc9131rdb/tlb.c +++ b/board/freescale/bsc9131rdb/tlb.c @@ -43,9 +43,14 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_8K, 1), + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#ifdef CONFIG_SPL_NAND_MINIMAL + SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_4K, 1), +#endif /* *I*G* - CCSRBAR (PA) */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c index 9263a47..0ec9a85 100644 --- a/board/freescale/bsc9132qds/tlb.c +++ b/board/freescale/bsc9132qds/tlb.c @@ -43,9 +43,14 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_8K, 1), + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#ifdef CONFIG_SPL_NAND_MINIMAL + SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_4K, 1), +#endif /* *I*G* - CCSRBAR (PA) */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 7a8690a..0a8159a 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -43,9 +43,14 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#ifdef CONFIG_SPL_NAND_MINIMAL SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_8K, 1), + 0, 10, BOOKE_PAGESZ_4K, 1), +#endif /* *I*G* - CCSRBAR */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,