Patchwork [U-Boot] powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL

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Submitter Prabhakar Kushwaha
Date May 7, 2013, 5:49 a.m.
Message ID <1367905795-9005-1-git-send-email-prabhakar@freescale.com>
Download mbox | patch
Permalink /patch/241980/
State Accepted
Delegated to: Andy Fleming
Headers show

Comments

Prabhakar Kushwaha - May 7, 2013, 5:49 a.m.
e500v2 processor does not support 8K page size TLB entries.

So create new TLB entry only during NAND SPL boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 Based upon git://git.denx.de/u-boot.git branch master

 This patch depends upon following patch set
  1) powerpc/mpc85xx:No NOR boot, do not compile IFC errata A003399
      http://patchwork.ozlabs.org/patch/236849/
  2) powerpc/mpc85xx: new SPL support for IFC NAND
      http://patchwork.ozlabs.org/patch/236850/
  3) board/p1010rdb:Add NAND boot support using new SPL format
     http://patchwork.ozlabs.org/patch/236851/
  4) board/bsc9131rdb:Add NAND boot support using new SPL format
     http://patchwork.ozlabs.org/patch/236852/
  5) board/bsc9132qds:Add NAND boot support using new SPL format
     http://patchwork.ozlabs.org/patch/236853/

 board/freescale/bsc9131rdb/tlb.c |   11 ++++++++---
 board/freescale/bsc9132qds/tlb.c |   11 ++++++++---
 board/freescale/p1010rdb/tlb.c   |    7 ++++++-
 3 files changed, 22 insertions(+), 7 deletions(-)
Andy Fleming - June 21, 2013, 8:44 p.m.
On Tue, May 07, 2013 at 11:19:55AM +0530, Prabhakar Kushwaha wrote:
> e500v2 processor does not support 8K page size TLB entries.
> 
> So create new TLB entry only during NAND SPL boot.
> 
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>

Applied, thanks!

Andy

Patch

diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c
index 243a38f..f65868f 100644
--- a/board/freescale/bsc9131rdb/tlb.c
+++ b/board/freescale/bsc9131rdb/tlb.c
@@ -43,9 +43,14 @@  struct fsl_e_tlb_entry tlb_table[] = {
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
-		SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
-			      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			      0, 0, BOOKE_PAGESZ_8K, 1),
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_MINIMAL
+	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
 
 	/* *I*G* - CCSRBAR (PA) */
 	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c
index 9263a47..0ec9a85 100644
--- a/board/freescale/bsc9132qds/tlb.c
+++ b/board/freescale/bsc9132qds/tlb.c
@@ -43,9 +43,14 @@  struct fsl_e_tlb_entry tlb_table[] = {
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
-		SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
-			      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			      0, 0, BOOKE_PAGESZ_8K, 1),
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_MINIMAL
+	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
 
 	/* *I*G* - CCSRBAR (PA) */
 	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index 7a8690a..0a8159a 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -43,9 +43,14 @@  struct fsl_e_tlb_entry tlb_table[] = {
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_MINIMAL
 	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_8K, 1),
+		      0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
 
 	/* *I*G* - CCSRBAR */
 	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,