From patchwork Tue May 7 05:17:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nobuhiro Iwamatsu X-Patchwork-Id: 241973 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 10C802C0117 for ; Tue, 7 May 2013 15:18:44 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758190Ab3EGFSe (ORCPT ); Tue, 7 May 2013 01:18:34 -0400 Received: from mail-pb0-f49.google.com ([209.85.160.49]:50585 "EHLO mail-pb0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751650Ab3EGFSc (ORCPT ); Tue, 7 May 2013 01:18:32 -0400 Received: by mail-pb0-f49.google.com with SMTP id rp8so133910pbb.8 for ; Mon, 06 May 2013 22:18:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=zhX8mdRg6z1Fzy6QjV+U1FOv9/Ioi4nu96apN39OSEs=; b=kXBI9aMcvJpss0uu0CIv2r5njd8yzxyZhbnVaZ6e6i+ArH/9jOpty70V/c1ZqL9a7A 3J/yXFh2EjXl+UPRzZoYu7DHPWTKssb4pny2SeFpaD3blvwJVB/IxZKYteGDKuWk+JOz dRBet+Cnq4eaxl2oYt+rReLJx3/5Kmp0aIqNKMbjVsy6Ds6t8rmCHLcRxdG8GIzIts5W RtHGbKG6nE1UuoJX4b0essCGFF4sZ98HXWotdzrWG7pM9EzYpY2xnpuXGKSKpW7WvL5c 2xH7cmZRYnIyK4mEEaY9IqJaaCQ73XLXd35+DRKMsouWymN1DkNavSSQcLGAyg8YQcAx rdhQ== X-Received: by 10.68.175.97 with SMTP id bz1mr657372pbc.37.1367903911828; Mon, 06 May 2013 22:18:31 -0700 (PDT) Received: from xps-iwamatsu.renesas.com (49.14.32.202.bf.2iij.net. [202.32.14.49]) by mx.google.com with ESMTPSA id em2sm26775526pbb.0.2013.05.06.22.18.29 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 06 May 2013 22:18:30 -0700 (PDT) From: Nobuhiro Iwamatsu To: netdev@vger.kernel.org Cc: yoshihiro.shimoda.uh@renesas.com, sergei.shtylyov@cogentembedded.com, Nobuhiro Iwamatsu Subject: [PATCH v3 9/9] net: sh-eth: Rewrite sh_eth_reset function Date: Tue, 7 May 2013 14:17:55 +0900 Message-Id: <1367903875-32606-9-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1367903875-32606-1-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> References: <1367903875-32606-1-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> X-Gm-Message-State: ALoCoQnMGZyVaOozUX7QzHhA9CVJ9IdVmu3gaY6zoqiO8o2zq5dYaw48Zh12VQBjdQ/uJ3pIbPI2 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This driver has sh_eth_reset function each CPU. And this function is almost the same. This is summarized in single function. Signed-off-by: Nobuhiro Iwamatsu --- V3: no change. V2: no change. drivers/net/ethernet/renesas/sh_eth.c | 194 +++++++++++---------------------- 1 file changed, 61 insertions(+), 133 deletions(-) diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c index 664a236..ee600f0 100644 --- a/drivers/net/ethernet/renesas/sh_eth.c +++ b/drivers/net/ethernet/renesas/sh_eth.c @@ -349,7 +349,6 @@ static void sh_eth_set_duplex(struct net_device *ndev) /* There is CPU dependent code */ #if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779) -#define SH_ETH_RESET_DEFAULT 1 static void sh_eth_set_rate(struct net_device *ndev) { struct sh_eth_private *mdp = netdev_priv(ndev); @@ -386,7 +385,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { .hw_swap = 1, }; #elif defined(CONFIG_CPU_SUBTYPE_SH7724) -#define SH_ETH_RESET_DEFAULT 1 static void sh_eth_set_rate(struct net_device *ndev) { @@ -427,7 +425,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { }; #elif defined(CONFIG_CPU_SUBTYPE_SH7757) #define SH_ETH_HAS_BOTH_MODULES 1 -static int sh_eth_check_reset(struct net_device *ndev); static void sh_eth_set_rate(struct net_device *ndev) { @@ -494,40 +491,6 @@ static void sh_eth_chip_reset_giga(struct net_device *ndev) } static int sh_eth_is_gether(struct sh_eth_private *mdp); -static int sh_eth_reset(struct net_device *ndev) -{ - struct sh_eth_private *mdp = netdev_priv(ndev); - int ret = 0; - - if (sh_eth_is_gether(mdp)) { - sh_eth_write(ndev, EDSR_ENALL, EDSR); - sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, - EDMR); - - ret = sh_eth_check_reset(ndev); - if (ret) - goto out; - - /* Table Init */ - sh_eth_write(ndev, 0x0, TDLAR); - sh_eth_write(ndev, 0x0, TDFAR); - sh_eth_write(ndev, 0x0, TDFXR); - sh_eth_write(ndev, 0x0, TDFFR); - sh_eth_write(ndev, 0x0, RDLAR); - sh_eth_write(ndev, 0x0, RDFAR); - sh_eth_write(ndev, 0x0, RDFXR); - sh_eth_write(ndev, 0x0, RDFFR); - } else { - sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, - EDMR); - mdelay(3); - sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, - EDMR); - } - -out: - return ret; -} static void sh_eth_set_rate_giga(struct net_device *ndev) { @@ -590,8 +553,6 @@ static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp) } #elif defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) -static int sh_eth_check_reset(struct net_device *ndev); -static void sh_eth_reset_hw_crc(struct net_device *ndev); static void sh_eth_chip_reset(struct net_device *ndev) { @@ -655,45 +616,8 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { #endif }; -static int sh_eth_reset(struct net_device *ndev) -{ - int ret = 0; - - sh_eth_write(ndev, EDSR_ENALL, EDSR); - sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR); - - ret = sh_eth_check_reset(ndev); - if (ret) - goto out; - - /* Table Init */ - sh_eth_write(ndev, 0x0, TDLAR); - sh_eth_write(ndev, 0x0, TDFAR); - sh_eth_write(ndev, 0x0, TDFXR); - sh_eth_write(ndev, 0x0, TDFFR); - sh_eth_write(ndev, 0x0, RDLAR); - sh_eth_write(ndev, 0x0, RDFAR); - sh_eth_write(ndev, 0x0, RDFXR); - sh_eth_write(ndev, 0x0, RDFFR); - - /* Reset HW CRC register */ - sh_eth_reset_hw_crc(ndev); - - /* Select MII mode */ - if (sh_eth_my_cpu_data.select_mii) - sh_eth_select_mii(ndev); -out: - return ret; -} - -static void sh_eth_reset_hw_crc(struct net_device *ndev) -{ - if (sh_eth_my_cpu_data.hw_crc) - sh_eth_write(ndev, 0x0, CSMR); -} #elif defined(CONFIG_ARCH_R8A7740) -static int sh_eth_check_reset(struct net_device *ndev); static void sh_eth_chip_reset(struct net_device *ndev) { @@ -706,31 +630,6 @@ static void sh_eth_chip_reset(struct net_device *ndev) sh_eth_select_mii(ndev); } -static int sh_eth_reset(struct net_device *ndev) -{ - int ret = 0; - - sh_eth_write(ndev, EDSR_ENALL, EDSR); - sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR); - - ret = sh_eth_check_reset(ndev); - if (ret) - goto out; - - /* Table Init */ - sh_eth_write(ndev, 0x0, TDLAR); - sh_eth_write(ndev, 0x0, TDFAR); - sh_eth_write(ndev, 0x0, TDFXR); - sh_eth_write(ndev, 0x0, TDFFR); - sh_eth_write(ndev, 0x0, RDLAR); - sh_eth_write(ndev, 0x0, RDFAR); - sh_eth_write(ndev, 0x0, RDFXR); - sh_eth_write(ndev, 0x0, RDFFR); - -out: - return ret; -} - static void sh_eth_set_rate(struct net_device *ndev) { struct sh_eth_private *mdp = netdev_priv(ndev); @@ -779,7 +678,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { }; #elif defined(CONFIG_CPU_SUBTYPE_SH7619) -#define SH_ETH_RESET_DEFAULT 1 static struct sh_eth_cpu_data sh_eth_my_cpu_data = { .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, @@ -789,7 +687,6 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = { .hw_swap = 1, }; #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) -#define SH_ETH_RESET_DEFAULT 1 static struct sh_eth_cpu_data sh_eth_my_cpu_data = { .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, .tsu = 1, @@ -825,36 +722,6 @@ static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) cd->tx_error_check = DEFAULT_TX_ERROR_CHECK; } -#if defined(SH_ETH_RESET_DEFAULT) -/* Chip Reset */ -static int sh_eth_reset(struct net_device *ndev) -{ - sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR); - mdelay(3); - sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR); - - return 0; -} -#else -static int sh_eth_check_reset(struct net_device *ndev) -{ - int ret = 0; - int cnt = 100; - - while (cnt > 0) { - if (!(sh_eth_read(ndev, EDMR) & 0x3)) - break; - mdelay(1); - cnt--; - } - if (cnt < 0) { - pr_err("Device reset fail\n"); - ret = -ETIMEDOUT; - } - return ret; -} -#endif - #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) static void sh_eth_set_receive_align(struct sk_buff *skb) { @@ -945,6 +812,67 @@ static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) return EDTRR_TRNS_ETHER; } +static int sh_eth_check_reset(struct net_device *ndev) +{ + int ret = 0; + int cnt = 100; + + while (cnt > 0) { + if (!(sh_eth_read(ndev, EDMR) & 0x3)) + break; + mdelay(1); + cnt--; + } + if (cnt < 0) { + pr_err("Device reset fail\n"); + ret = -ETIMEDOUT; + } + return ret; +} + +static int sh_eth_reset(struct net_device *ndev) +{ + struct sh_eth_private *mdp = netdev_priv(ndev); + int ret = 0; + + if (sh_eth_is_gether(mdp)) { + sh_eth_write(ndev, EDSR_ENALL, EDSR); + sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, + EDMR); + + ret = sh_eth_check_reset(ndev); + if (ret) + goto out; + + /* Table Init */ + sh_eth_write(ndev, 0x0, TDLAR); + sh_eth_write(ndev, 0x0, TDFAR); + sh_eth_write(ndev, 0x0, TDFXR); + sh_eth_write(ndev, 0x0, TDFFR); + sh_eth_write(ndev, 0x0, RDLAR); + sh_eth_write(ndev, 0x0, RDFAR); + sh_eth_write(ndev, 0x0, RDFXR); + sh_eth_write(ndev, 0x0, RDFFR); + + /* Reset HW CRC register */ + if (mdp->cd->hw_crc) + sh_eth_write(ndev, 0x0, CSMR); + + /* Select MII mode */ + if (mdp->cd->select_mii) + sh_eth_select_mii(ndev); + } else { + sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, + EDMR); + mdelay(3); + sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, + EDMR); + } + +out: + return ret; +} + struct bb_info { void (*set_gate)(void *addr); struct mdiobb_ctrl ctrl;