From patchwork Mon May 6 13:17:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 241648 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 032272C00EC for ; Mon, 6 May 2013 23:19:28 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CAF9C4A2AD; Mon, 6 May 2013 15:19:26 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8p1EG1fRjv9X; Mon, 6 May 2013 15:19:26 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 17FD84A2B5; Mon, 6 May 2013 15:19:11 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 16DC04A2A7 for ; Mon, 6 May 2013 15:19:07 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WR1f+B8dv-ZA for ; Mon, 6 May 2013 15:19:02 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-oa0-f45.google.com (mail-oa0-f45.google.com [209.85.219.45]) by theia.denx.de (Postfix) with ESMTPS id 367BA4A26F for ; Mon, 6 May 2013 15:18:56 +0200 (CEST) Received: by mail-oa0-f45.google.com with SMTP id o17so3481875oag.18 for ; Mon, 06 May 2013 06:18:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=++tuOPYqzZHQVe7X9MlQRLL5BXUimWX76Ni1IVji8ak=; b=lVlEBMlZ0JtP91OnPtCdDFn7gNfFMT50kBEbwVYVuHkc2ZW5rFOMsi/2mMT1mWD10K 9UQ3ZPa0wcvMOQbDisMSUGNRktwsg9KMO1l3srD98q8+3riSwIFpRjB/uCwzvvd+epwE GUlh5KoT/MoaddQT4Suds/8qY54ftG2vE0CRP8gBafHWzB8DNFPElpb+LLl02tkN+n95 JqfL4cL9JvFrcskVlOkIrux6pXi2jc+nnk1jXw6GjmrwwKKTFHCvN940UbRbZkmu3CdB pwBcABhZkD4ZjNlu7RbsZq4dMhmbeoJeoCdR+KdBfNIXnkK7j7WZUI0BtNwhf9pcXbrA XRjQ== X-Received: by 10.60.120.34 with SMTP id kz2mr5409182oeb.17.1367846335492; Mon, 06 May 2013 06:18:55 -0700 (PDT) Received: from slackpad.drs.calxeda.com (f053080141.adsl.alicedsl.de. [78.53.80.141]) by mx.google.com with ESMTPSA id x10sm5081475oes.6.2013.05.06.06.18.52 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 06 May 2013 06:18:55 -0700 (PDT) From: Andre Przywara To: trini@ti.com, albert.u.boot@aribaud.net Date: Mon, 6 May 2013 15:17:46 +0200 Message-Id: <1367846270-1827-3-git-send-email-andre.przywara@linaro.org> X-Mailer: git-send-email 1.7.12.1 In-Reply-To: <1367846270-1827-1-git-send-email-andre.przywara@linaro.org> References: <1367846270-1827-1-git-send-email-andre.przywara@linaro.org> X-Gm-Message-State: ALoCoQkpmh8ikHPgiB7ieLAQj6NxeDuywW51kX0ZrHrZoow7hRxj9TMS1qsDN+KWeYMTaMuJgmt/ Cc: peter.maydell@linaro.org, geoff.levand@linaro.org, cdall@cs.columbia.edu, marc.zyngier@arm.com, agraf@suse.de, u-boot@lists.denx.de, kvmarm@lists.cs.columbia.edu Subject: [U-Boot] [PATCH 2/6] ARM: add assembly routine to switch to non-secure state X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de While actually switching to non-secure state is one thing, the more important part of this process is to make sure that we still have full access to the interrupt controller (GIC). The GIC is fully aware of secure vs. non-secure state, some registers are banked, others may be configured to be accessible from secure state only. To be as generic as possible, we get the GIC memory mapped address based on the PERIPHBASE register. We check explicitly for ARM Cortex-A7 and A15 cores, assuming an A9 otherwise, as for those cores we know the offsets for the GIC CPU interface from the PERIPHBASE content. Other cores could be added as needed. With the GIC accessible, we: a) allow private interrupts to be delivered to the core (GICD_IGROUPR0 = 0xFFFFFFFF) b) enable the CPU interface (GICC_CTLR[0] = 1) c) set the priority filter to allow non-secure interrupts (GICC_PMR = 0x80) After having switched to non-secure state, we also enable the non-secure GIC CPU interface, since this register is banked. Also we allow access to all coprocessor interfaces from non-secure state by writing the appropriate bits in the NSACR register. For reasons obvious later we only use caller saved registers r0-r3. Signed-off-by: Andre Przywara --- arch/arm/cpu/armv7/start.S | 47 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index da48b36..e63e892 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -572,3 +572,50 @@ fiq: #endif /* CONFIG_USE_IRQ */ #endif /* CONFIG_SPL_BUILD */ + +#ifdef CONFIG_ARMV7_VIRT +/* Routine to initialize GIC CPU interface and switch to nonsecure state. + */ +.globl _nonsec_gic_switch +_nonsec_gic_switch: + mrc p15, 4, r2, c15, c0, 0 @ r2 = PERIPHBASE + add r3, r2, #0x1000 @ GIC dist i/f offset + mvn r1, #0 + str r1, [r3, #0x80] @ allow private interrupts + + mrc p15, 0, r0, c0, c0, 0 @ MIDR + bfc r0, #16, #8 @ mask out variant, arch + bfc r0, #0, #4 @ and revision + movw r1, #0xc070 + movt r1, #0x4100 + cmp r0, r1 @ check for Cortex-A7 + orr r1, #0xf0 + cmpne r0, r1 @ check for Cortex-A15 + movne r1, #0x100 @ GIC CPU offset for A9 + moveq r1, #0x2000 @ GIC CPU offset for A15/A7 + add r3, r2, r1 @ r3 = GIC CPU i/f addr + + mov r1, #1 + str r1, [r3, #0] @ set GICC_CTLR[enable] + mov r1, #0x80 + str r1, [r3, #4] @ set GICC_PIMR[7] + + movw r1, #0x3fff + movt r1, #0x0006 + mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec + + ldr r1, =_start + mcr p15, 0, r1, c12, c0, 0 @ set VBAR + mcr p15, 0, r1, c12, c0, 1 @ set MVBAR + + isb + smc #0 @ call into MONITOR mode + isb @ clobbers r0 and r1 + + mov r1, #1 + str r1, [r3, #0] @ set GICC_CTLR[enable] + add r2, r2, #0x1000 @ GIC dist i/f offset + str r1, [r2] @ allow private interrupts + + mov pc, lr +#endif /* CONFIG_ARMV7_VIRT */