Patchwork Patch of consistent VMX cpu flag

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Submitter 李春奇
Date May 4, 2013, 7:59 a.m.
Message ID <CABpY8M+gqkt_xHCm105_MyDfM7PLU3-O0uq7ObXa+KoNWMTkfQ@mail.gmail.com>
Download mbox | patch
Permalink /patch/241435/
State New
Headers show

Comments

李春奇 - May 4, 2013, 7:59 a.m.
Hi all,
There's a patch for some simulated Intel CPU with default flag of VMX, now
only core(2)duo are with VMX flag by default.

Add default ext_features of CPUID_EXT_VMX to the following CPUs:
kvm64, kvm32, Penryn, Nehalem, Westmere, SandyBridge, Haswell.

Other CPUs of AMD and lower versions of Intel CPU without VMX support don't
add this feature by default.

Patch:

         .ext3_features = CPUID_EXT3_LAHF_LM,
         .xlevel = 0x8000000A,
@@ -667,7 +667,7 @@ static x86_def_t builtin_x86_defs[] = {
              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
              CPUID_DE | CPUID_FP87,
         .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 |
-             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
+             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3 |
CPUID_EXT_VMX,
         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL |
CPUID_EXT2_NX,
         .ext3_features = CPUID_EXT3_LAHF_LM,
         .xlevel = 0x8000000A,
@@ -687,7 +687,7 @@ static x86_def_t builtin_x86_defs[] = {
              CPUID_DE | CPUID_FP87,
         .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42
|
              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
-             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
+             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | CPUID_EXT_VMX,
         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL |
CPUID_EXT2_NX,
         .ext3_features = CPUID_EXT3_LAHF_LM,
         .xlevel = 0x8000000A,
@@ -709,7 +709,7 @@ static x86_def_t builtin_x86_defs[] = {
              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
              CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
-             CPUID_EXT_SSE3,
+             CPUID_EXT_SSE3 | CPUID_EXT_VMX,
         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX
|
              CPUID_EXT2_SYSCALL,
         .ext3_features = CPUID_EXT3_LAHF_LM,
@@ -733,7 +733,7 @@ static x86_def_t builtin_x86_defs[] = {
              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA |
CPUID_EXT_MOVBE |
-             CPUID_EXT_PCID,
+             CPUID_EXT_PCID | CPUID_EXT_VMX,
         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX
|
              CPUID_EXT2_SYSCALL,
         .ext3_features = CPUID_EXT3_LAHF_LM,
Jan Kiszka - May 4, 2013, 8:08 a.m.
On 2013-05-04 09:59, 李春奇 <Arthur Chunqi Li> wrote:
> Hi all,
> There's a patch for some simulated Intel CPU with default flag of VMX, now
> only core(2)duo are with VMX flag by default.
> 
> Add default ext_features of CPUID_EXT_VMX to the following CPUs:
> kvm64, kvm32, Penryn, Nehalem, Westmere, SandyBridge, Haswell.
> 
> Other CPUs of AMD and lower versions of Intel CPU without VMX support don't
> add this feature by default.
> 
> Patch:

Please have a look at http://wiki.qemu.org/Contribute/SubmitAPatch
regarding how to format a patch.

Moreover, your mail client had line-wrapping enabled which ruins the
patch. And you are sending mixed plain/html mails, but only plain-text
is acceptable.

Jan

> 
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index e2302d8..7b659f7 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -490,7 +490,7 @@ static x86_def_t builtin_x86_defs[] = {
>              CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
>              CPUID_PSE36,
>          /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
> -        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
> +        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_VMX,
>          /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
>          .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
>              CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
> @@ -522,7 +522,7 @@ static x86_def_t builtin_x86_defs[] = {
>          .stepping = 1,
>          .features = PPRO_FEATURES |
>              CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
> -        .ext_features = CPUID_EXT_SSE3,
> +        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_VMX,
>          .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
>          .ext3_features = 0,
>          .xlevel = 0x80000008,
> @@ -648,7 +648,7 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>               CPUID_DE | CPUID_FP87,
>          .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3
> |
> -             CPUID_EXT_SSE3,
> +             CPUID_EXT_SSE3 | CPUID_EXT_VMX,
>          .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX |
> CPUID_EXT2_SYSCALL,
>          .ext3_features = CPUID_EXT3_LAHF_LM,
>          .xlevel = 0x8000000A,
> @@ -667,7 +667,7 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>               CPUID_DE | CPUID_FP87,
>          .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
> CPUID_EXT_SSE41 |
> -             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
> +             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3 |
> CPUID_EXT_VMX,
>          .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL |
> CPUID_EXT2_NX,
>          .ext3_features = CPUID_EXT3_LAHF_LM,
>          .xlevel = 0x8000000A,
> @@ -687,7 +687,7 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_DE | CPUID_FP87,
>          .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42
> |
>               CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
> -             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
> +             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | CPUID_EXT_VMX,
>          .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL |
> CPUID_EXT2_NX,
>          .ext3_features = CPUID_EXT3_LAHF_LM,
>          .xlevel = 0x8000000A,
> @@ -709,7 +709,7 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
>               CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
>               CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
> -             CPUID_EXT_SSE3,
> +             CPUID_EXT_SSE3 | CPUID_EXT_VMX,
>          .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX
> |
>               CPUID_EXT2_SYSCALL,
>          .ext3_features = CPUID_EXT3_LAHF_LM,
> @@ -733,7 +733,7 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
>               CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
>               CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA |
> CPUID_EXT_MOVBE |
> -             CPUID_EXT_PCID,
> +             CPUID_EXT_PCID | CPUID_EXT_VMX,
>          .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX
> |
>               CPUID_EXT2_SYSCALL,
>          .ext3_features = CPUID_EXT3_LAHF_LM,
>
Andreas Färber - May 4, 2013, 8:33 a.m.
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Am 04.05.2013 10:08, schrieb Jan Kiszka:
> On 2013-05-04 09:59, 李春奇 <Arthur Chunqi Li> wrote:
>> Hi all, There's a patch for some simulated Intel CPU with default
>> flag of VMX, now only core(2)duo are with VMX flag by default.
>> 
>> Add default ext_features of CPUID_EXT_VMX to the following CPUs: 
>> kvm64, kvm32, Penryn, Nehalem, Westmere, SandyBridge, Haswell.
>> 
>> Other CPUs of AMD and lower versions of Intel CPU without VMX
>> support don't add this feature by default.
>> 
>> Patch:
> 
> Please have a look at http://wiki.qemu.org/Contribute/SubmitAPatch 
> regarding how to format a patch.
> 
> Moreover, your mail client had line-wrapping enabled which ruins
> the patch. And you are sending mixed plain/html mails, but only
> plain-text is acceptable.

Further, you need to rebase your patch on yesterday's code.

It is not acceptable to simply add CPUID flags to the fields, you need
to assure that pc-i440fx-1.4 and earlier machines maintain the old
values for migration compatibility. See Eduardo's and my pending
series on the mailing list.

Regards,
Andreas

>> diff --git a/target-i386/cpu.c b/target-i386/cpu.c index
>> e2302d8..7b659f7 100644 --- a/target-i386/cpu.c +++
>> b/target-i386/cpu.c @@ -490,7 +490,7 @@ static x86_def_t
>> builtin_x86_defs[] = { CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 
>> CPUID_PSE36, /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ -
>> .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16, +
>> .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_VMX, 
>> /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 
>> .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | 
>> CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, @@ -522,7
>> +522,7 @@ static x86_def_t builtin_x86_defs[] = { .stepping = 1, 
>> .features = PPRO_FEATURES | CPUID_MTRR | CPUID_CLFLUSH |
>> CPUID_MCA | CPUID_PSE36, -        .ext_features =
>> CPUID_EXT_SSE3, +        .ext_features = CPUID_EXT_SSE3 |
>> CPUID_EXT_VMX, .ext2_features = PPRO_FEATURES &
>> CPUID_EXT2_AMD_ALIASES, .ext3_features = 0, .xlevel =
>> 0x80000008, @@ -648,7 +648,7 @@ static x86_def_t
>> builtin_x86_defs[] = { CPUID_MCE | CPUID_PAE | CPUID_MSR |
>> CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, .ext_features =
>> CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | -
>> CPUID_EXT_SSE3, +             CPUID_EXT_SSE3 | CPUID_EXT_VMX, 
>> .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | 
>> CPUID_EXT2_SYSCALL, .ext3_features = CPUID_EXT3_LAHF_LM, .xlevel
>> = 0x8000000A, @@ -667,7 +667,7 @@ static x86_def_t
>> builtin_x86_defs[] = { CPUID_MCE | CPUID_PAE | CPUID_MSR |
>> CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, .ext_features =
>> CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | -
>> CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, +
>> CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3 | 
>> CPUID_EXT_VMX, .ext2_features = CPUID_EXT2_LM |
>> CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .ext3_features =
>> CPUID_EXT3_LAHF_LM, .xlevel = 0x8000000A, @@ -687,7 +687,7 @@
>> static x86_def_t builtin_x86_defs[] = { CPUID_DE | CPUID_FP87, 
>> .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT |
>> CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 |
>> CPUID_EXT_SSSE3 | -             CPUID_EXT_PCLMULQDQ |
>> CPUID_EXT_SSE3, +             CPUID_EXT_PCLMULQDQ |
>> CPUID_EXT_SSE3 | CPUID_EXT_VMX, .ext2_features = CPUID_EXT2_LM |
>> CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .ext3_features =
>> CPUID_EXT3_LAHF_LM, .xlevel = 0x8000000A, @@ -709,7 +709,7 @@
>> static x86_def_t builtin_x86_defs[] = { 
>> CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 
>> CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 
>> CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | -
>> CPUID_EXT_SSE3, +             CPUID_EXT_SSE3 | CPUID_EXT_VMX, 
>> .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
>> CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, .ext3_features =
>> CPUID_EXT3_LAHF_LM, @@ -733,7 +733,7 @@ static x86_def_t
>> builtin_x86_defs[] = { CPUID_EXT_SSE41 | CPUID_EXT_CX16 |
>> CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 
>> CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 
>> -             CPUID_EXT_PCID, +             CPUID_EXT_PCID |
>> CPUID_EXT_VMX, .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP
>> | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, .ext3_features =
>> CPUID_EXT3_LAHF_LM,
>> 
> 
> 


- -- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
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Patch

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index e2302d8..7b659f7 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -490,7 +490,7 @@  static x86_def_t builtin_x86_defs[] = {
             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
             CPUID_PSE36,
         /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
-        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
+        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_VMX,
         /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
@@ -522,7 +522,7 @@  static x86_def_t builtin_x86_defs[] = {
         .stepping = 1,
         .features = PPRO_FEATURES |
             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
-        .ext_features = CPUID_EXT_SSE3,
+        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_VMX,
         .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
         .ext3_features = 0,
         .xlevel = 0x80000008,
@@ -648,7 +648,7 @@  static x86_def_t builtin_x86_defs[] = {
              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
              CPUID_DE | CPUID_FP87,
         .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3
|
-             CPUID_EXT_SSE3,
+             CPUID_EXT_SSE3 | CPUID_EXT_VMX,
         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,