Patchwork [U-Boot,v3,9/9] fpga: Remove all CONFIG_SYS_* fpga related options

login
register
mail settings
Submitter Michal Simek
Date May 3, 2013, 7:14 a.m.
Message ID <598fb0688ef194f6215ab95f1b57fcd605d5ccbb.1367565248.git.michal.simek@xilinx.com>
Download mbox | patch
Permalink /patch/241233/
State Accepted
Delegated to: Albert ARIBAUD
Headers show

Comments

Michal Simek - May 3, 2013, 7:14 a.m.
All these macros are completely unused by any code.
CONFIG_FPGA is not a bitfield anymore.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in v3:
- New patch in this series

Changes in v2: None

 include/altera.h              | 17 -----------------
 include/configs/M54455EVB.h   |  2 +-
 include/configs/MERGERBOX.h   |  2 +-
 include/configs/MVBC_P.h      |  2 +-
 include/configs/MVBLM7.h      |  2 +-
 include/configs/MVSMR.h       |  2 +-
 include/configs/omap3_mvblx.h |  2 +-
 include/fpga.h                | 10 ----------
 include/lattice.h             |  3 ---
 include/xilinx.h              | 24 ------------------------
 10 files changed, 6 insertions(+), 60 deletions(-)

--
1.8.2.1

Patch

diff --git a/include/altera.h b/include/altera.h
index 7a2bece..6aad5ee 100644
--- a/include/altera.h
+++ b/include/altera.h
@@ -27,23 +27,6 @@ 
 #ifndef _ALTERA_H_
 #define _ALTERA_H_

-/* Altera Model definitions
- *********************************************************************/
-#define CONFIG_SYS_ACEX1K		CONFIG_SYS_FPGA_DEV( 0x1 )
-#define CONFIG_SYS_CYCLON2		CONFIG_SYS_FPGA_DEV( 0x2 )
-#define CONFIG_SYS_STRATIX_II		CONFIG_SYS_FPGA_DEV( 0x4 )
-
-#define CONFIG_SYS_ALTERA_ACEX1K	(CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_ACEX1K)
-#define CONFIG_SYS_ALTERA_CYCLON2	(CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_CYCLON2)
-#define CONFIG_SYS_ALTERA_STRATIX_II	(CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_STRATIX_II)
-/* Add new models here */
-
-/* Altera Interface definitions
- *********************************************************************/
-#define CONFIG_SYS_ALTERA_IF_PS	CONFIG_SYS_FPGA_IF( 0x1 )	/* passive serial */
-#define CONFIG_SYS_ALTERA_IF_FPP	CONFIG_SYS_FPGA_IF( 0x2 )	/* fast passive parallel */
-/* Add new interfaces here */
-
 typedef enum {				/* typedef Altera_iface */
 	min_altera_iface_type,		/* insert all new types after this */
 	passive_serial,			/* serial data and external clock */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 1bc2c5a..536b755 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -238,7 +238,7 @@ 

 /* FPGA - Spartan 2 */
 /* experiment
-#define CONFIG_FPGA		CONFIG_SYS_SPARTAN3
+#define CONFIG_FPGA
 #define CONFIG_FPGA_COUNT	1
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_CHECK_CTRLC
diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h
index c296e3c..30fb6c2 100644
--- a/include/configs/MERGERBOX.h
+++ b/include/configs/MERGERBOX.h
@@ -606,7 +606,7 @@ 
  * FPGA
  */
 #define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA		CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2

diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h
index 6850965..7271468 100644
--- a/include/configs/MVBC_P.h
+++ b/include/configs/MVBC_P.h
@@ -310,7 +310,7 @@ 

 #undef FPGA_DEBUG
 #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA		CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA	1
 #define CONFIG_FPGA_CYCLON2	1
 #define CONFIG_FPGA_COUNT	1
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index a99ad3c..a9c00ac 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -499,7 +499,7 @@ 
 	""

 #define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA		CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2

diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h
index bf2f44e..5d2ff14 100644
--- a/include/configs/MVSMR.h
+++ b/include/configs/MVSMR.h
@@ -280,7 +280,7 @@ 

 #undef FPGA_DEBUG
 #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA		CONFIG_SYS_XILINX_SPARTAN2
+#define CONFIG_FPGA
 #define CONFIG_FPGA_XILINX	1
 #define CONFIG_FPGA_SPARTAN2	1
 #define CONFIG_FPGA_COUNT	1
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
index 376a3d0..f9adc01 100644
--- a/include/configs/omap3_mvblx.h
+++ b/include/configs/omap3_mvblx.h
@@ -273,7 +273,7 @@ 
 #endif /* (CONFIG_CMD_NET) */

 #define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA          CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
diff --git a/include/fpga.h b/include/fpga.h
index ebefba8..38e9018 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -31,16 +31,6 @@ 
 #define CONFIG_MAX_FPGA_DEVICES		5
 #endif

-/* CONFIG_FPGA bit assignments */
-#define CONFIG_SYS_FPGA_MAN(x)		(x)
-#define CONFIG_SYS_FPGA_DEV(x)		((x) << 8 )
-#define CONFIG_SYS_FPGA_IF(x)		((x) << 16 )
-
-/* FPGA Manufacturer bits in CONFIG_FPGA */
-#define CONFIG_SYS_FPGA_XILINX		CONFIG_SYS_FPGA_MAN( 0x1 )
-#define CONFIG_SYS_FPGA_ALTERA		CONFIG_SYS_FPGA_MAN( 0x2 )
-
-
 /* fpga_xxxx function return value definitions */
 #define FPGA_SUCCESS		0
 #define FPGA_FAIL		-1
diff --git a/include/lattice.h b/include/lattice.h
index 6a2cf93..49871da 100644
--- a/include/lattice.h
+++ b/include/lattice.h
@@ -278,9 +278,6 @@  typedef struct {
 	char		*desc;	/* description string */
 } Lattice_desc;			/* end, typedef Altera_desc */

-/* Lattice Model Type */
-#define CONFIG_SYS_XP2		CONFIG_SYS_FPGA_DEV(0x1)
-
 /* Board specific implementation specific function types */
 typedef void (*Lattice_jtag_init)(void);
 typedef void (*Lattice_jtag_set_tdi)(int v);
diff --git a/include/xilinx.h b/include/xilinx.h
index bcfe76d..9a64771 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -27,30 +27,6 @@ 
 #ifndef _XILINX_H_
 #define _XILINX_H_

-/* Xilinx Model definitions
- *********************************************************************/
-#define CONFIG_SYS_SPARTAN2			CONFIG_SYS_FPGA_DEV( 0x1 )
-#define CONFIG_SYS_VIRTEX_E			CONFIG_SYS_FPGA_DEV( 0x2 )
-#define CONFIG_SYS_VIRTEX2			CONFIG_SYS_FPGA_DEV( 0x4 )
-#define CONFIG_SYS_SPARTAN3			CONFIG_SYS_FPGA_DEV( 0x8 )
-#define CONFIG_SYS_ZYNQ				CONFIG_SYS_FPGA_DEV(0x10)
-#define CONFIG_SYS_XILINX_SPARTAN2	(CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN2)
-#define CONFIG_SYS_XILINX_VIRTEX_E	(CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX_E)
-#define CONFIG_SYS_XILINX_VIRTEX2	(CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX2)
-#define CONFIG_SYS_XILINX_SPARTAN3	(CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN3)
-#define CONFIG_SYS_XILINX_ZYNQ	(CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_ZYNQ)
-/* XXX - Add new models here */
-
-
-/* Xilinx Interface definitions
- *********************************************************************/
-#define CONFIG_SYS_XILINX_IF_SS	CONFIG_SYS_FPGA_IF( 0x1 )	/* slave serial		*/
-#define CONFIG_SYS_XILINX_IF_MS	CONFIG_SYS_FPGA_IF( 0x2 )	/* master serial	*/
-#define CONFIG_SYS_XILINX_IF_SP	CONFIG_SYS_FPGA_IF( 0x4 )	/* slave parallel	*/
-#define CONFIG_SYS_XILINX_IF_JTAG	CONFIG_SYS_FPGA_IF( 0x8 )	/* jtag			*/
-#define CONFIG_SYS_XILINX_IF_MSM	CONFIG_SYS_FPGA_IF( 0x10 )	/* master selectmap	*/
-#define CONFIG_SYS_XILINX_IF_SSM	CONFIG_SYS_FPGA_IF( 0x20 )	/* slave selectmap	*/
-
 /* Xilinx types
  *********************************************************************/
 typedef enum {			/* typedef Xilinx_iface */