Patchwork [U-Boot,v3,7/7] mxs: spl_mem_init: Change EMI port priority

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Submitter Fabio Estevam
Date May 2, 2013, 10:44 p.m.
Message ID <1367534661-13502-8-git-send-email-festevam@gmail.com>
Download mbox | patch
Permalink /patch/241114/
State Superseded
Headers show

Comments

Fabio Estevam - May 2, 2013, 10:44 p.m.
From: Fabio Estevam <fabio.estevam@freescale.com>

FSL bootlets code set the PORT_PRIORITY_ORDER field of register HW_EMI_CTRL
as 0x2, which means:

PORT0231 = 0x02 Priority Order: AXI0, AHB2, AHB3, AHB1

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v2:
- None
Changes since v1:
- None

 arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index bf58058..5d881da 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -286,7 +286,7 @@  static void mx23_mem_init(void)
 	early_delay(20000);
 
 	/* Adjust EMI port priority. */
-	clrsetbits_le32(0x80020000, 0x1f << 16, 0x8);
+	clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
 	early_delay(20000);
 
 	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);