From patchwork Thu May 2 22:44:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 241113 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A677E2C00C9 for ; Fri, 3 May 2013 08:45:54 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D8CE74A3C9; Fri, 3 May 2013 00:45:52 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qqvZ4o9sVs4w; Fri, 3 May 2013 00:45:52 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 476254A37F; Fri, 3 May 2013 00:45:13 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D9F704A379 for ; Fri, 3 May 2013 00:45:09 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MxgCWweImLSD for ; Fri, 3 May 2013 00:45:04 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-gh0-f180.google.com (mail-gh0-f180.google.com [209.85.160.180]) by theia.denx.de (Postfix) with ESMTPS id 424184A362 for ; Fri, 3 May 2013 00:44:50 +0200 (CEST) Received: by mail-gh0-f180.google.com with SMTP id f18so178655ghb.11 for ; Thu, 02 May 2013 15:44:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=HWHwE0Z7Bc+oN6NeN2mfaqAmX7Lf2USj4lNdceypG6E=; b=fgMSno508ihzl/lvJ++REYVlEw3nyQc3a2tdOfYhwfwDZWINMcXmUfWx8iEtQCkRNQ oIFKA/vV1fylW8GW9SyvaQsq39u8TsQHn7o/MiKd9d9hMbiaO5v9x/H36QvZ+Xcy0QqG AD6WEbPROrtsrxCBirXD3+pmxZnfb68nRgHYOCf14C4wya56NWEN3ijLHhq1nK7StpKN NUjksJqYe2YYvDVjfgW5/gxl9kb9E2yJUZNTzVJoOA0v8kZ1rhEWpqDuYw9Sr0IZtxzD rRSFRw43sHBQWIFkyB/28W7d6X4w/x2upMwbBP4ySJhJdVH6yqjR2rOmHRdy/tu6eYSI T5AA== X-Received: by 10.236.4.137 with SMTP id 9mr6702161yhj.203.1367534689952; Thu, 02 May 2013 15:44:49 -0700 (PDT) Received: from localhost.localdomain ([187.106.36.101]) by mx.google.com with ESMTPSA id n15sm16093242yhi.2.2013.05.02.15.44.47 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 02 May 2013 15:44:49 -0700 (PDT) From: Fabio Estevam To: sbabic@denx.de Date: Thu, 2 May 2013 19:44:19 -0300 Message-Id: <1367534661-13502-6-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1367534661-13502-1-git-send-email-festevam@gmail.com> References: <1367534661-13502-1-git-send-email-festevam@gmail.com> Cc: marex@denx.de, u-boot@lists.denx.de, otavio@ossystems.com.br, Fabio Estevam Subject: [U-Boot] [PATCH v3 5/7] mxs: spl_mem_init: Remove erroneous DDR setting X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Fabio Estevam On mx23 there is no 'DRAM init complete' in register HW_DRAM_CTL18. Remove this erroneous setting. Signed-off-by: Fabio Estevam --- Changes since v2: - None Changes since v1: - Newly introduced as the previous patch is now splitted. arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 300da0a..df25535 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -279,10 +279,6 @@ static void mx23_mem_init(void) setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19); setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11); - - /* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */ - while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10))) - ; } #endif