From patchwork Thu May 2 22:44:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 241112 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 203D52C00BD for ; Fri, 3 May 2013 08:45:45 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 58B664A3A5; Fri, 3 May 2013 00:45:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LAO5qpkT8DH8; Fri, 3 May 2013 00:45:42 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F372A4A37C; Fri, 3 May 2013 00:45:09 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BFFA44A345 for ; Fri, 3 May 2013 00:45:04 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XQzNLdvYw-np for ; Fri, 3 May 2013 00:44:59 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yh0-f41.google.com (mail-yh0-f41.google.com [209.85.213.41]) by theia.denx.de (Postfix) with ESMTPS id 076314A366 for ; Fri, 3 May 2013 00:44:48 +0200 (CEST) Received: by mail-yh0-f41.google.com with SMTP id i72so186818yha.0 for ; Thu, 02 May 2013 15:44:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=YNIxfh7F9rAbDLBwnTRwpby2QL9v04e+9IP46OhAhJM=; b=ywAntLJs/moag6Hx9JTu6dzkKm4ueVSJ4YI6xjolEawdj/M5jyDKUiveLLLo4FzIkB fOKvxEaK1CW0o39Jy7FCBeZ/DCdb9CfrbWpfksL7/SIkGp7YrvH6r6XTJWIvA7lEeZBo n+KhyE3lvaYCDdGh2Xqbyp6MHnp60bxxp2LsL/ZRIDItdReo1UBfOCC/1L8PfhE5LagR bKDkU6GBgR70wcBvndD8t9gPy9LlDKveP3ZUb/ue0nnD0wZF6JUpFd9UYTM+N27eO+Y1 rC6DPfJjc7Cg7mbEWgfj47M+kiJp9OEzFLAPcPUAYWpYlMMJI5KeUcCZg1mK+YB5eI6d znyw== X-Received: by 10.236.93.107 with SMTP id k71mr6694597yhf.91.1367534687428; Thu, 02 May 2013 15:44:47 -0700 (PDT) Received: from localhost.localdomain ([187.106.36.101]) by mx.google.com with ESMTPSA id n15sm16093242yhi.2.2013.05.02.15.44.45 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 02 May 2013 15:44:46 -0700 (PDT) From: Fabio Estevam To: sbabic@denx.de Date: Thu, 2 May 2013 19:44:18 -0300 Message-Id: <1367534661-13502-5-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1367534661-13502-1-git-send-email-festevam@gmail.com> References: <1367534661-13502-1-git-send-email-festevam@gmail.com> Cc: marex@denx.de, u-boot@lists.denx.de, otavio@ossystems.com.br, Fabio Estevam Subject: [U-Boot] [PATCH v3 4/7] mxs: spl_mem_init: Fix comment about start bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Fabio Estevam Start bit is part of HW_DRAM_CTL8 register, so fix the comment. Signed-off-by: Fabio Estevam --- Changes since v2: - None Changes since v1: - Newly introduced as the previous patch is now splitted. arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 4950490..300da0a 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -267,7 +267,7 @@ static void mx23_mem_init(void) initialize_dram_values(); - /* Set START bit in DRAM_CTL16 */ + /* Set START bit in DRAM_CTL8 */ setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16); clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);