From patchwork Thu May 2 14:04:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 241020 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5863E2C0085 for ; Fri, 3 May 2013 00:30:54 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BEECF4A17F; Thu, 2 May 2013 16:30:51 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IzY-ssStxf2Q; Thu, 2 May 2013 16:30:51 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EABE44A2DE; Thu, 2 May 2013 16:28:47 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CFEA24A141 for ; Thu, 2 May 2013 16:24:27 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ocNR0Y1feDhk for ; Thu, 2 May 2013 16:24:04 +0200 (CEST) X-Greylist: delayed 926 seconds by postgrey-1.27 at theia; Thu, 02 May 2013 16:20:41 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 BL_NJABL=ERR(-1.5) (only DNSBL check requested) Received: from co9outboundpool.messaging.microsoft.com (co9ehsobe003.messaging.microsoft.com [207.46.163.26]) by theia.denx.de (Postfix) with ESMTPS id 0741D4A2D9 for ; Thu, 2 May 2013 16:20:34 +0200 (CEST) Received: from mail120-co9-R.bigfish.com (10.236.132.232) by CO9EHSOBE018.bigfish.com (10.236.130.81) with Microsoft SMTP Server id 14.1.225.23; Thu, 2 May 2013 14:05:01 +0000 Received: from mail120-co9 (localhost [127.0.0.1]) by mail120-co9-R.bigfish.com (Postfix) with ESMTP id CD55C720629; Thu, 2 May 2013 14:05:01 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h1fc6h1ee6h1de0h1fdah1202h1e76h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1155h) Received: from mail120-co9 (localhost.localdomain [127.0.0.1]) by mail120-co9 (MessageSwitch) id 1367503499138700_21740; Thu, 2 May 2013 14:04:59 +0000 (UTC) Received: from CO9EHSMHS019.bigfish.com (unknown [10.236.132.253]) by mail120-co9.bigfish.com (Postfix) with ESMTP id 1F025380073; Thu, 2 May 2013 14:04:59 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO9EHSMHS019.bigfish.com (10.236.130.29) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 2 May 2013 14:04:58 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.2.328.11; Thu, 2 May 2013 14:04:57 +0000 Received: from fabio-Latitude-E6410.am.freescale.net ([10.29.244.56]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r42E4OiU026112; Thu, 2 May 2013 07:04:56 -0700 From: Fabio Estevam To: Date: Thu, 2 May 2013 11:04:21 -0300 Message-ID: <1367503462-24742-8-git-send-email-fabio.estevam@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1367503462-24742-1-git-send-email-fabio.estevam@freescale.com> References: <1367503462-24742-1-git-send-email-fabio.estevam@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: marex@denx.de, u-boot@lists.denx.de, Fabio@theia.denx.de, Estevam , otavio@ossystems.com.br Subject: [U-Boot] [PATCH v2 7/8] mxs: spl_mem_init: Skip the initialization of some DRAM_CTL registers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as per FSL bootlets code. mx23 Reference Manual mark HW_DRAM_CTL27 and HW_DRAM_CTL28 as "reserved". HW_DRAM_CTL8 is setup as the last element. So skip the initialization of these DRAM_CTL registers. Signed-off-by: Fabio Estevam --- Changes since v1: - To avoid polluting the mx28 case, separate the function definition in mx23 and for mx28. arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index df25535..bf58058 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -110,6 +110,7 @@ __weak void mxs_adjust_memory_params(uint32_t *dram_vals) { } +#ifdef CONFIG_MX28 static void initialize_dram_values(void) { int i; @@ -118,15 +119,26 @@ static void initialize_dram_values(void) for (i = 0; i < ARRAY_SIZE(dram_vals); i++) writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); +} +#else +static void initialize_dram_values(void) +{ + int i; + + mxs_adjust_memory_params(dram_vals); + + for (i = 0; i < ARRAY_SIZE(dram_vals); i++) { + if (!(i == 8 || i == 27 || i == 28 || i == 35)) + writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); + } -#ifdef CONFIG_MX23 /* * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last * element to be set */ writel((1 << 24), MXS_DRAM_BASE + (4 * 8)); -#endif } +#endif static void mxs_mem_init_clock(void) {