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[U-Boot,v2,6/8] mxs: spl_mem_init: Remove erroneous DDR setting

Message ID 1367503462-24742-7-git-send-email-fabio.estevam@freescale.com
State Superseded
Headers show

Commit Message

Fabio Estevam May 2, 2013, 2:04 p.m. UTC 
On mx23 there is no 'DRAM init complete' in register HW_DRAM_CTL18.

Remove this erroneous setting.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1:
- Newly introduced as the previous patch is now splitted.

 arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c |    4 ----
 1 file changed, 4 deletions(-)
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Patch

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 300da0a..df25535 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -279,10 +279,6 @@  static void mx23_mem_init(void)
 
 	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
 	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
-
-	/* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
-	while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
-		;
 }
 #endif