From patchwork Thu May 2 13:35:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 241000 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E57CB2C00A1 for ; Thu, 2 May 2013 23:50:12 +1000 (EST) Received: from localhost ([::1]:44391 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UXttj-0005pl-7I for incoming@patchwork.ozlabs.org; Thu, 02 May 2013 09:50:11 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48957) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UXtgK-00035B-6c for qemu-devel@nongnu.org; Thu, 02 May 2013 09:36:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UXtg4-0004Yc-Du for qemu-devel@nongnu.org; Thu, 02 May 2013 09:36:20 -0400 Received: from cantor2.suse.de ([195.135.220.15]:46627 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UXtg4-0004Wt-2N for qemu-devel@nongnu.org; Thu, 02 May 2013 09:36:04 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id A6AD8A55E7; Thu, 2 May 2013 15:36:02 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Thu, 2 May 2013 15:35:46 +0200 Message-Id: <1367501755-32272-21-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1367501755-32272-1-git-send-email-afaerber@suse.de> References: <1367501755-32272-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: Igor Mammedov , Anthony Liguori , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH 20/29] target-i386: Move APIC to ICC bus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Igor Mammedov It allows APIC to be hotplugged. * map APIC's mmio at board level if it is present * do not register mmio region for each APIC, since only one is used/mapped Signed-off-by: Igor Mammedov Signed-off-by: Andreas Färber --- hw/cpu/icc_bus.c | 10 ++++++++++ hw/i386/pc.c | 13 +++++++++++-- hw/intc/apic_common.c | 18 ++++++++++++------ include/hw/cpu/icc_bus.h | 3 +++ include/hw/i386/apic_internal.h | 6 +++--- target-i386/cpu.c | 16 +++------------- 6 files changed, 42 insertions(+), 24 deletions(-) diff --git a/hw/cpu/icc_bus.c b/hw/cpu/icc_bus.c index 3ac8eeb..73a1dc9 100644 --- a/hw/cpu/icc_bus.c +++ b/hw/cpu/icc_bus.c @@ -80,6 +80,7 @@ typedef struct ICCBridgeState { /*< public >*/ ICCBus icc_bus; + MemoryRegion apic_container; } ICCBridgeState; #define ICC_BRIGDE(obj) OBJECT_CHECK(ICCBridgeState, (obj), TYPE_ICC_BRIDGE) @@ -87,8 +88,17 @@ typedef struct ICCBridgeState { static void icc_bridge_init(Object *obj) { ICCBridgeState *s = ICC_BRIGDE(obj); + SysBusDevice *sb = SYS_BUS_DEVICE(obj); qbus_create_inplace(&s->icc_bus, TYPE_ICC_BUS, DEVICE(s), "icc"); + + /* Do not change order of registering regions, + * APIC must be first registered region, board maps it by 0 index + */ + memory_region_init(&s->apic_container, "icc-apic-container", + APIC_SPACE_SIZE); + sysbus_init_mmio(sb, &s->apic_container); + s->icc_bus.apic_address_space = &s->apic_container; } static const TypeInfo icc_bridge_info = { diff --git a/hw/i386/pc.c b/hw/i386/pc.c index c4c4e35..28f958d 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -53,6 +53,7 @@ #include "qemu/bitmap.h" #include "qemu/config-file.h" #include "hw/acpi/acpi.h" +#include "hw/cpu/icc_bus.h" /* debug PC/ISA interrupts */ //#define DEBUG_IRQ @@ -921,6 +922,7 @@ static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) { int i; + X86CPU *cpu = NULL; Error *error = NULL; /* init CPUs */ @@ -933,14 +935,21 @@ void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) } for (i = 0; i < smp_cpus; i++) { - pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), - icc_bridge, &error); + cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), + icc_bridge, &error); if (error) { fprintf(stderr, "%s\n", error_get_pretty(error)); error_free(error); exit(1); } } + + /* map APIC MMIO area if CPU has APIC */ + if (cpu && cpu->env.apic_state) { + /* XXX: what if the base changes? */ + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, + APIC_DEFAULT_ADDRESS, 0x1000); + } } void pc_acpi_init(const char *default_dsdt) diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index e0ae07a..b03e904 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -21,6 +21,8 @@ #include "hw/i386/apic_internal.h" #include "trace.h" #include "sysemu/kvm.h" +#include "hw/qdev.h" +#include "hw/sysbus.h" static int apic_irq_delivered; bool apic_report_tpr_access; @@ -282,12 +284,13 @@ static int apic_load_old(QEMUFile *f, void *opaque, int version_id) return 0; } -static int apic_init_common(SysBusDevice *dev) +static int apic_init_common(ICCDevice *dev) { APICCommonState *s = APIC_COMMON(dev); APICCommonClass *info; static DeviceState *vapic; static int apic_no; + static bool mmio_registered; if (apic_no >= MAX_APICS) { return -1; @@ -296,8 +299,11 @@ static int apic_init_common(SysBusDevice *dev) info = APIC_COMMON_GET_CLASS(s); info->init(s); - - sysbus_init_mmio(dev, &s->io_memory); + if (!mmio_registered) { + ICCBus *b = ICC_BUS(qdev_get_parent_bus(DEVICE(dev))); + memory_region_add_subregion(b->apic_address_space, 0, &s->io_memory); + mmio_registered = true; + } /* Note: We need at least 1M to map the VAPIC option ROM */ if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && @@ -375,19 +381,19 @@ static Property apic_properties_common[] = { static void apic_common_class_init(ObjectClass *klass, void *data) { - SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass); + ICCDeviceClass *idc = ICC_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); dc->vmsd = &vmstate_apic_common; dc->reset = apic_reset_common; dc->no_user = 1; dc->props = apic_properties_common; - sc->init = apic_init_common; + idc->init = apic_init_common; } static const TypeInfo apic_common_type = { .name = TYPE_APIC_COMMON, - .parent = TYPE_SYS_BUS_DEVICE, + .parent = TYPE_ICC_DEVICE, .instance_size = sizeof(APICCommonState), .class_size = sizeof(APICCommonClass), .class_init = apic_common_class_init, diff --git a/include/hw/cpu/icc_bus.h b/include/hw/cpu/icc_bus.h index d728a7d..b550070 100644 --- a/include/hw/cpu/icc_bus.h +++ b/include/hw/cpu/icc_bus.h @@ -22,6 +22,7 @@ #ifndef ICC_BUS_H #define ICC_BUS_H +#include "exec/memory.h" #include "hw/qdev-core.h" #define TYPE_ICC_BUS "icc-bus" @@ -37,6 +38,8 @@ typedef struct ICCBus { /*< private >*/ BusState parent_obj; /*< public >*/ + + MemoryRegion *apic_address_space; } ICCBus; #define ICC_BUS(obj) OBJECT_CHECK(ICCBus, (obj), TYPE_ICC_BUS) diff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_internal.h index aac6290..1b0a7fb 100644 --- a/include/hw/i386/apic_internal.h +++ b/include/hw/i386/apic_internal.h @@ -21,7 +21,7 @@ #define QEMU_APIC_INTERNAL_H #include "exec/memory.h" -#include "hw/sysbus.h" +#include "hw/cpu/icc_bus.h" #include "qemu/timer.h" /* APIC Local Vector Table */ @@ -78,7 +78,7 @@ typedef struct APICCommonState APICCommonState; typedef struct APICCommonClass { - SysBusDeviceClass parent_class; + ICCDeviceClass parent_class; void (*init)(APICCommonState *s); void (*set_base)(APICCommonState *s, uint64_t val); @@ -92,7 +92,7 @@ typedef struct APICCommonClass } APICCommonClass; struct APICCommonState { - SysBusDevice busdev; + ICCDevice busdev; MemoryRegion io_memory; X86CPU *cpu; diff --git a/target-i386/cpu.c b/target-i386/cpu.c index a165bcf..bba41fe 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -41,10 +41,10 @@ #endif #include "sysemu/sysemu.h" +#include "hw/qdev-properties.h" #include "hw/cpu/icc_bus.h" #ifndef CONFIG_USER_ONLY #include "hw/xen/xen.h" -#include "hw/sysbus.h" #include "hw/i386/apic_internal.h" #endif @@ -2131,6 +2131,7 @@ static void mce_init(X86CPU *cpu) static void x86_cpu_apic_create(X86CPU *cpu, Error **errp) { CPUX86State *env = &cpu->env; + DeviceState *dev = DEVICE(cpu); APICCommonState *apic; const char *apic_type = "apic"; @@ -2140,7 +2141,7 @@ static void x86_cpu_apic_create(X86CPU *cpu, Error **errp) apic_type = "xen-apic"; } - env->apic_state = qdev_try_create(NULL, apic_type); + env->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type); if (env->apic_state == NULL) { error_setg(errp, "APIC device '%s' could not be created", apic_type); return; @@ -2157,7 +2158,6 @@ static void x86_cpu_apic_create(X86CPU *cpu, Error **errp) static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) { CPUX86State *env = &cpu->env; - static int apic_mapped; if (env->apic_state == NULL) { return; @@ -2168,16 +2168,6 @@ static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) object_get_typename(OBJECT(env->apic_state))); return; } - - /* XXX: mapping more APICs at the same memory location */ - if (apic_mapped == 0) { - /* NOTE: the APIC is directly connected to the CPU - it is not - on the global memory bus. */ - /* XXX: what if the base changes? */ - sysbus_mmio_map_overlap(SYS_BUS_DEVICE(env->apic_state), 0, - APIC_DEFAULT_ADDRESS, 0x1000); - apic_mapped = 1; - } } #else static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)