From patchwork Wed May 1 21:44:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 240821 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 0DBE72C009F for ; Thu, 2 May 2013 07:47:10 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E814C4A359; Wed, 1 May 2013 23:46:56 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CyTqensRSTmB; Wed, 1 May 2013 23:46:56 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 246194A2B4; Wed, 1 May 2013 23:46:07 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2C7384A262 for ; Wed, 1 May 2013 23:45:57 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id b1FSpP7JtU0O for ; Wed, 1 May 2013 23:45:52 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ye0-f175.google.com (mail-ye0-f175.google.com [209.85.213.175]) by theia.denx.de (Postfix) with ESMTPS id 5D6034A227 for ; Wed, 1 May 2013 23:45:26 +0200 (CEST) Received: by mail-ye0-f175.google.com with SMTP id q7so347762yen.34 for ; Wed, 01 May 2013 14:45:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=A2Vr2egonU5GcjtJOApmPncV8vWYXMTDASYCoIMCgq0=; b=TBCPkLFs2AxPq735FHUzSGPcx2M6pesQAP+q34LwNUxvsb87NhpXm53ccdNAwhh5P3 SxThUrc+mthN0p/ZyVEqk9MiME8MmgxBmOpBZYAIXfNaG8vAgiDkXps+9EMc4eahtrXn r0atNkFqsL7mRVdegBehNWfw+RDW0CJmfqqrfqb4otz8l32SH4nR3VFaujp9J4Ioc5aG nkN03qc98ObNoRmuWnO6omcznGDnWXcl+P0F4oDZsiKy7dN5whNlNHf+jhDMrTTaeyIX YOAoVmAdW3fjbMiEZKAgBcz7mhJlOdXjR3b/h6MJNzvVJK+z7fOC85d+E7Fz2oM55+8I SwTw== X-Received: by 10.236.19.196 with SMTP id n44mr3166815yhn.65.1367444725779; Wed, 01 May 2013 14:45:25 -0700 (PDT) Received: from localhost.localdomain ([187.106.36.101]) by mx.google.com with ESMTPSA id y24sm3504941yhn.20.2013.05.01.14.45.23 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 01 May 2013 14:45:25 -0700 (PDT) From: Fabio Estevam To: sbabic@denx.de Date: Wed, 1 May 2013 18:44:49 -0300 Message-Id: <1367444689-31301-10-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1367444689-31301-1-git-send-email-festevam@gmail.com> References: <1367444689-31301-1-git-send-email-festevam@gmail.com> Cc: marex@denx.de, u-boot@lists.denx.de, Fabio Estevam , otavio@ossystems.com.br Subject: [U-Boot] [PATCH 9/9] mxs: spl_mem_init: Change EMI port priority X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Fabio Estevam FSL bootlets code set the PORT_PRIORITY_ORDER field of register HW_EMI_CTRL as 0x2, which means: PORT0231 = 0x02 Priority Order: AXI0, AHB2, AHB3, AHB1 Signed-off-by: Fabio Estevam --- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index f500851..68b9587 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -274,7 +274,7 @@ static void mx23_mem_init(void) early_delay(20000); /* Adjust EMI port priority. */ - clrsetbits_le32(0x80020000, 0x1f << 16, 0x8); + clrsetbits_le32(0x80020000, 0x1f << 16, 0x2); early_delay(20000); setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);