From patchwork Wed May 1 21:44:47 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 240817 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 7782E2C00C8 for ; Thu, 2 May 2013 07:46:36 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 563B34A1C7; Wed, 1 May 2013 23:46:26 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jOPViPBti0Bk; Wed, 1 May 2013 23:46:26 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1FE6B4A1FC; Wed, 1 May 2013 23:45:51 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 67F514A260 for ; Wed, 1 May 2013 23:45:44 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id n9VomJGVAIFE for ; Wed, 1 May 2013 23:45:39 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 BL_NJABL=ERR(-1.5) (only DNSBL check requested) Received: from mail-ye0-f172.google.com (mail-ye0-f172.google.com [209.85.213.172]) by theia.denx.de (Postfix) with ESMTPS id 4E8564A1E4 for ; Wed, 1 May 2013 23:45:21 +0200 (CEST) Received: by mail-ye0-f172.google.com with SMTP id m15so358489yen.17 for ; Wed, 01 May 2013 14:45:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=fbSYY72ek/ZDWPl7JuNiS0P8d+9jk/XT6d3XnsTFp40=; b=Vst4uCEAcax3o7XZnehusuhKebcfhDlvLlqrcVQatyAnawfpdtwk1U/hk7TaWZvMri xTftcMt6SFFgpPWF60VA9aN8G9mCQpao51wpkJiAHN5G05yEhcCwutlojSn5zOXLvcQy SwV64DWh2h9MVXsZ8mqj5KV0p9v0goI4X+cBWq85TgPLastqB6pJNmzcVa3vZDlEqG0y g1tkbrMZI4oVFJ+/4+6Ed3YUTL9C82EZ2VD+YtilLfNVCpQ2wIXk8krOxejvYU5uW5QS bzpjO6uzbS7SPlYR8Z45wfa8GDFQOyRkMYMP/EQi3s+hac09hw7e3obD20+oCPXn/VY6 xnqA== X-Received: by 10.236.112.73 with SMTP id x49mr2991212yhg.145.1367444720963; Wed, 01 May 2013 14:45:20 -0700 (PDT) Received: from localhost.localdomain ([187.106.36.101]) by mx.google.com with ESMTPSA id y24sm3504941yhn.20.2013.05.01.14.45.18 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 01 May 2013 14:45:20 -0700 (PDT) From: Fabio Estevam To: sbabic@denx.de Date: Wed, 1 May 2013 18:44:47 -0300 Message-Id: <1367444689-31301-8-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1367444689-31301-1-git-send-email-festevam@gmail.com> References: <1367444689-31301-1-git-send-email-festevam@gmail.com> Cc: marex@denx.de, u-boot@lists.denx.de, Fabio Estevam , otavio@ossystems.com.br Subject: [U-Boot] [PATCH 7/9] mxs: spl_mem_init: Remove unneeded DRAM configurations X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Fabio Estevam There is no need to write to DRAM_CTL8 register prior to nitialize_dram_values(). Fix a comment related to writing to DRAM_CTL8. Also, DRAM_CTL18 register on mx23 does not contain DRAM init complete bit, so remove this setting as this is also not done by FSL bootlets code. Signed-off-by: Fabio Estevam --- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 1c509d6..cde883d 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -262,12 +262,9 @@ static void mx23_mem_init(void) * Configure the DRAM registers */ - /* Clear START and SREFRESH bit from DRAM_CTL8 */ - clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8)); - initialize_dram_values(); - /* Set START bit in DRAM_CTL16 */ + /* Set START bit in DRAM_CTL8 */ setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16); clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17); @@ -279,10 +276,6 @@ static void mx23_mem_init(void) setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19); setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11); - - /* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */ - while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10))) - ; } #endif