Patchwork [U-Boot,7/9] mxs: spl_mem_init: Remove unneeded DRAM configurations

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Submitter Fabio Estevam
Date May 1, 2013, 9:44 p.m.
Message ID <1367444689-31301-8-git-send-email-festevam@gmail.com>
Download mbox | patch
Permalink /patch/240817/
State Changes Requested
Delegated to: Stefano Babic
Headers show

Comments

Fabio Estevam - May 1, 2013, 9:44 p.m.
From: Fabio Estevam <fabio.estevam@freescale.com>

There is no need to write to DRAM_CTL8 register prior to nitialize_dram_values().

Fix a comment related to writing to DRAM_CTL8.

Also, DRAM_CTL18 register on mx23 does not contain DRAM init complete bit, so
remove this setting as this is also not done by FSL bootlets code.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c |    9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)
Marek Vasut - May 1, 2013, 11:29 p.m.
Dear Fabio Estevam,

> From: Fabio Estevam <fabio.estevam@freescale.com>
> 
> There is no need to write to DRAM_CTL8 register prior to
> nitialize_dram_values().
> 
> Fix a comment related to writing to DRAM_CTL8.
> 
> Also, DRAM_CTL18 register on mx23 does not contain DRAM init complete bit,
> so remove this setting as this is also not done by FSL bootlets code.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
>  arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c |    9 +--------
>  1 file changed, 1 insertion(+), 8 deletions(-)
> 
> diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 1c509d6..cde883d 100644
> --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> @@ -262,12 +262,9 @@ static void mx23_mem_init(void)
>  	 * Configure the DRAM registers
>  	 */
> 
> -	/* Clear START and SREFRESH bit from DRAM_CTL8 */
> -	clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8));
> -

Do you not need to stop the DRAM if it's already running? Like after a software 
reset?

>  	initialize_dram_values();
> 
> -	/* Set START bit in DRAM_CTL16 */
> +	/* Set START bit in DRAM_CTL8 */
>  	setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
> 
>  	clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
> @@ -279,10 +276,6 @@ static void mx23_mem_init(void)
> 
>  	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
>  	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
> -
> -	/* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
> -	while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
> -		;
>  }
>  #endif

Best regards,
Marek Vasut
Fabio Estevam - May 1, 2013, 11:54 p.m.
On Wed, May 1, 2013 at 8:29 PM, Marek Vasut <marex@denx.de> wrote:

> Do you not need to stop the DRAM if it's already running? Like after a software
> reset?

I don't think this is needed. FSL bootlets code does not do this.
Marek Vasut - May 2, 2013, 12:15 a.m.
Dear Fabio Estevam,

> On Wed, May 1, 2013 at 8:29 PM, Marek Vasut <marex@denx.de> wrote:
> > Do you not need to stop the DRAM if it's already running? Like after a
> > software reset?
> 
> I don't think this is needed. FSL bootlets code does not do this.

You'll end up messing with configuration registers on already-running RAM. That 
doesn't really make sense and I suspect it can result in some weird behavior.

Best regards,
Marek Vasut
Fabio Estevam - May 2, 2013, 12:24 a.m.
On Wed, May 1, 2013 at 9:15 PM, Marek Vasut <marex@denx.de> wrote:

> You'll end up messing with configuration registers on already-running RAM. That

HW_DRAM_CTL08, bit 16 (START) is 0 (inactive) after a reset, so no
need to turn off the RAM.

Patch

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 1c509d6..cde883d 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -262,12 +262,9 @@  static void mx23_mem_init(void)
 	 * Configure the DRAM registers
 	 */
 
-	/* Clear START and SREFRESH bit from DRAM_CTL8 */
-	clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8));
-
 	initialize_dram_values();
 
-	/* Set START bit in DRAM_CTL16 */
+	/* Set START bit in DRAM_CTL8 */
 	setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
 
 	clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
@@ -279,10 +276,6 @@  static void mx23_mem_init(void)
 
 	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
 	setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
-
-	/* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
-	while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
-		;
 }
 #endif