From patchwork Wed May 1 21:44:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 240815 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 19F092C00C8 for ; Thu, 2 May 2013 07:46:16 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AC01E4A214; Wed, 1 May 2013 23:46:10 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MvKx04eVXo9b; Wed, 1 May 2013 23:46:10 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1954D4A247; Wed, 1 May 2013 23:45:42 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4E3E24A22E for ; Wed, 1 May 2013 23:45:39 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PkFYecgmIr2F for ; Wed, 1 May 2013 23:45:34 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-gg0-f171.google.com (mail-gg0-f171.google.com [209.85.161.171]) by theia.denx.de (Postfix) with ESMTPS id 5AB8C4A1D3 for ; Wed, 1 May 2013 23:45:15 +0200 (CEST) Received: by mail-gg0-f171.google.com with SMTP id j5so348559ggn.16 for ; Wed, 01 May 2013 14:45:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=YyGLIyxXXO+lorB3N8EPM3R4SG+VUhbYsSrzO2Y/Yro=; b=UHqJ/DrSIFdpYWyYZDwSfx6dnB3IhR2dsdMCKMeAXqpUHTu7MFHpQnJ0K1Dz/xY7+s UE46F6eKbxXEeEmJkm+RnuXd+QfiZeDWCBfPnZX2b1SUf4D2gw8q9rXpWLB9TdRQIx4y lY9vIt1A1Zi/P7BlWBH0lzMikN15mH+H7QR03WBbZ+8i+rwTvtcDre8K+8/owDeItu+U G/YeqMGQ3OmpgyYj4ZP4itnAHN6b5h7e3UErVLMCVzOTrAbmatJInvKUiLPc81UCyeuy 41FInIQzC34leUmLVav1LdzN4ZkqADCiiNih3uIgNpxaFSEvehXNttkqGfhib475TabG KRFw== X-Received: by 10.236.31.66 with SMTP id l42mr3072799yha.143.1367444714124; Wed, 01 May 2013 14:45:14 -0700 (PDT) Received: from localhost.localdomain ([187.106.36.101]) by mx.google.com with ESMTPSA id y24sm3504941yhn.20.2013.05.01.14.45.12 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 01 May 2013 14:45:13 -0700 (PDT) From: Fabio Estevam To: sbabic@denx.de Date: Wed, 1 May 2013 18:44:44 -0300 Message-Id: <1367444689-31301-5-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1367444689-31301-1-git-send-email-festevam@gmail.com> References: <1367444689-31301-1-git-send-email-festevam@gmail.com> Cc: marex@denx.de, u-boot@lists.denx.de, Fabio Estevam , otavio@ossystems.com.br Subject: [U-Boot] [PATCH 4/9] mx23_olinuxino: Fix DDR pin iomux settings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Fabio Estevam Registers HW_PINCTRL_DRIVE9, HW_PINCTRL_DRIVE10, HW_PINCTRL_DRIVE11, HW_PINCTRL_DRIVE12, HW_PINCTRL_DRIVE13 and HW_PINCTRL_DRIVE14 control the drive strength and the voltage selection for the DDR pins. The reset values of the voltage selection pins are '1', which is marked as 'reserved' in the mx23 reference manual. Clear these bits for proper operation of DDR. Also change MUX_CONFIG_EMI, which results in better stability and match the bootlets code from Freescale. Signed-off-by: Fabio Estevam --- board/olimex/mx23_olinuxino/spl_boot.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c index a96c293..5a43677 100644 --- a/board/olimex/mx23_olinuxino/spl_boot.c +++ b/board/olimex/mx23_olinuxino/spl_boot.c @@ -30,7 +30,7 @@ #include #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_16MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP MXS_PAD_12MA const iomux_cfg_t iomux_setup[] = { /* DUART */ @@ -103,5 +103,16 @@ const iomux_cfg_t iomux_setup[] = { void board_init_ll(void) { + struct mxs_pinctrl_regs *pinctrl = + (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; + + /* Clear the voltage bits for EMI pins as the reset value is invalid */ + writel(0, &pinctrl->drive9); + writel(0, &pinctrl->drive10); + writel(0, &pinctrl->drive11); + writel(0, &pinctrl->drive12); + writel(0, &pinctrl->drive13); + writel(0, &pinctrl->drive14); + writel(0, &pinctrl->drive9); mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); }