From patchwork Wed May 1 19:53:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Christophe Dubois X-Patchwork-Id: 240807 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0EBB82C00F1 for ; Thu, 2 May 2013 05:54:32 +1000 (EST) Received: from localhost ([::1]:56804 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UXd6j-0007r9-U7 for incoming@patchwork.ozlabs.org; Wed, 01 May 2013 15:54:29 -0400 Received: from eggs.gnu.org ([208.118.235.92]:41753) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UXd6D-0007qu-2B for qemu-devel@nongnu.org; Wed, 01 May 2013 15:54:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UXd6B-0004kF-72 for qemu-devel@nongnu.org; Wed, 01 May 2013 15:53:56 -0400 Received: from zose-mta15.web4all.fr ([178.33.204.94]:52353) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UXd6A-0004jh-Ur for qemu-devel@nongnu.org; Wed, 01 May 2013 15:53:55 -0400 Received: from localhost (localhost [127.0.0.1]) by zose-mta15.web4all.fr (Postfix) with ESMTP id F2ACF3C03F; Wed, 1 May 2013 21:53:50 +0200 (CEST) Received: from zose-mta15.web4all.fr ([127.0.0.1]) by localhost (zose-mta15.web4all.fr [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id x1jTUicE6CnB; Wed, 1 May 2013 21:53:50 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by zose-mta15.web4all.fr (Postfix) with ESMTP id 1170B3C046; Wed, 1 May 2013 21:53:50 +0200 (CEST) X-Virus-Scanned: amavisd-new at zose-mta15.web4all.fr Received: from zose-mta15.web4all.fr ([127.0.0.1]) by localhost (zose-mta15.web4all.fr [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id LtmbowHFbssf; Wed, 1 May 2013 21:53:49 +0200 (CEST) Received: from localhost.localdomain (smm49-1-78-235-240-156.fbx.proxad.net [78.235.240.156]) by zose-mta15.web4all.fr (Postfix) with ESMTPSA id 8F6483C03F; Wed, 1 May 2013 21:53:49 +0200 (CEST) From: Jean-Christophe DUBOIS To: qemu-devel@nongnu.org Date: Wed, 1 May 2013 21:53:46 +0200 Message-Id: <1367438026-27573-1-git-send-email-jcd@tribudubois.net> X-Mailer: git-send-email 1.8.1.2 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 178.33.204.94 Cc: peter.maydell@linaro.org, peter.chubb@nicta.com.au, Jean-Christophe DUBOIS Subject: [Qemu-devel] [PATCH 1/2] Add i.MX I2C device emulator. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Jean-Christophe DUBOIS --- default-configs/arm-softmmu.mak | 2 + hw/i2c/Makefile.objs | 1 + hw/i2c/imx_i2c.c | 374 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 377 insertions(+) create mode 100644 hw/i2c/imx_i2c.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index b3a0207..a20f112 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -81,3 +81,5 @@ CONFIG_VERSATILE_PCI=y CONFIG_VERSATILE_I2C=y CONFIG_SDHCI=y + +CONFIG_IMX_I2C=y diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs index 648278e..d27bbaa 100644 --- a/hw/i2c/Makefile.objs +++ b/hw/i2c/Makefile.objs @@ -4,4 +4,5 @@ common-obj-$(CONFIG_ACPI) += smbus_ich9.o common-obj-$(CONFIG_APM) += pm_smbus.o common-obj-$(CONFIG_BITBANG_I2C) += bitbang_i2c.o common-obj-$(CONFIG_EXYNOS4) += exynos4210_i2c.o +common-obj-$(CONFIG_IMX_I2C) += imx_i2c.o obj-$(CONFIG_OMAP) += omap_i2c.o diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c new file mode 100644 index 0000000..30d3f5c --- /dev/null +++ b/hw/i2c/imx_i2c.c @@ -0,0 +1,374 @@ +/* + * i.MX I2C Bus Serial Interface Emulation + * + * Copyright (C) 2013 Jean-Christophe Dubois. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + * + */ + +#include "hw/sysbus.h" +#include "hw/i2c/i2c.h" + +#ifndef IMX_I2C_DEBUG +#define IMX_I2C_DEBUG 0 +#endif + +#define TYPE_IMX_I2C "imx.i2c" +#define IMX_I2C(obj) \ + OBJECT_CHECK(imx_i2c_state, (obj), TYPE_IMX_I2C) + +/* i.MX I2C memory map */ +#define IMX_I2C_MEM_SIZE 0x14 +#define IADR_ADDR 0x00 /* address register */ +#define IFDR_ADDR 0x04 /* frequency divider register */ +#define I2CR_ADDR 0x08 /* control register */ +#define I2SR_ADDR 0x0c /* status register */ +#define I2DR_ADDR 0x10 /* data register */ + +#define IADR_MASK 0xFE +#define IADR_RESET 0 + +#define IFDR_MASK 0x3F +#define IFDR_RESET 0 + +#define I2CR_IEN (1 << 7) +#define I2CR_IIEN (1 << 6) +#define I2CR_MSTA (1 << 5) +#define I2CR_MTX (1 << 4) +#define I2CR_TXAK (1 << 3) +#define I2CR_RSTA (1 << 2) +#define I2CR_MASK 0xFC +#define I2CR_RESET 0 + +#define I2SR_ICF (1 << 7) +#define I2SR_IAAF (1 << 6) +#define I2SR_IBB (1 << 5) +#define I2SR_IAL (1 << 4) +#define I2SR_SRW (1 << 2) +#define I2SR_IIF (1 << 1) +#define I2SR_RXAK (1 << 0) +#define I2SR_MASK 0xE9 +#define I2SR_RESET 0x81 + +#define I2DR_MASK 0xFF +#define I2DR_RESET 0 + +#define ADDR_RESET 0xFF00 + +#if IMX_I2C_DEBUG +#define DPRINT(fmt, args...) \ + do { fprintf(stderr, "%s: "fmt, __func__, ## args); } while (0) + +static const char *imx_i2c_get_regname(unsigned offset) +{ + switch (offset) { + case IADR_ADDR: + return "IADR"; + case IFDR_ADDR: + return "IFDR"; + case I2CR_ADDR: + return "I2CR"; + case I2SR_ADDR: + return "I2SR"; + case I2DR_ADDR: + return "I2DR"; + default: + return "[?]"; + } +} + +#else +#define DPRINT(fmt, args...) do { } while (0) +#endif + +typedef struct imx_i2c_state { + SysBusDevice busdev; + MemoryRegion iomem; + i2c_bus *bus; + qemu_irq irq; + + uint16_t address; + + uint16_t iadr; + uint16_t ifdr; + uint16_t i2cr; + uint16_t i2sr; + uint16_t i2dr_read; + uint16_t i2dr_write; +} imx_i2c_state; + +static inline bool imx_i2c_is_enabled(imx_i2c_state *s) +{ + return (s->i2cr & I2CR_IEN); +} + +static inline bool imx_i2c_interrupt_is_enabled(imx_i2c_state *s) +{ + return (s->i2cr & I2CR_IIEN); +} + +static inline bool imx_i2c_is_master(imx_i2c_state *s) +{ + return (s->i2cr & I2CR_MSTA); +} + +static inline bool imx_i2c_direction_is_tx(imx_i2c_state *s) +{ + return (s->i2cr & I2CR_MTX); +} + +static void imx_i2c_reset(DeviceState *d) +{ + imx_i2c_state *s = FROM_SYSBUS(imx_i2c_state, SYS_BUS_DEVICE(d)); + + if (s->address != ADDR_RESET) { + i2c_end_transfer(s->bus); + } + + s->address = ADDR_RESET; + s->iadr = IADR_RESET; + s->ifdr = IFDR_RESET; + s->i2cr = I2CR_RESET; + s->i2sr = I2SR_RESET; + s->i2dr_read = I2DR_RESET; + s->i2dr_write = I2DR_RESET; +} + +static inline void imx_i2c_raise_interrupt(imx_i2c_state *s) +{ + /* + * raise an interrupt if the device is enabled and it is configured + * to generate some interrupts. + */ + if (imx_i2c_is_enabled(s) && imx_i2c_interrupt_is_enabled(s)) { + s->i2sr |= I2SR_IIF; + qemu_irq_raise(s->irq); + } +} + +static uint64_t imx_i2c_read(void *opaque, hwaddr offset, + unsigned size) +{ + imx_i2c_state *s = (imx_i2c_state *)opaque; + uint16_t value; + + switch (offset) { + case IADR_ADDR: + value = s->iadr; + break; + case IFDR_ADDR: + value = s->ifdr; + break; + case I2CR_ADDR: + value = s->i2cr; + break; + case I2SR_ADDR: + value = s->i2sr; + break; + case I2DR_ADDR: + value = s->i2dr_read; + if (imx_i2c_is_master(s)) { // master mode + int ret; + + if (s->address == ADDR_RESET) { + // something is wrong as the address is not set + DPRINT("Trying to read with specifying the slave address\n"); + } + + if ((ret = i2c_recv(s->bus)) >= 0) { + s->i2dr_read = ret; + imx_i2c_raise_interrupt(s); + } else { + DPRINT("read failed for device 0x%02x\n" s->address); + s->i2dr_read = 0xff; + } + } else { // slave mode + } + break; + default: + hw_error("%s: Bad address 0x%x\n", __func__, (int)offset); + break; + } + + DPRINT("read %s [0x%02x] -> 0x%02x\n", imx_i2c_get_regname(offset), + (unsigned int)offset, value); + + return (uint64_t)value; +} + +static void imx_i2c_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + imx_i2c_state *s = (imx_i2c_state *)opaque; + uint16_t v = value & 0xff; + + DPRINT("write %s [0x%02x] <- 0x%02x\n", imx_i2c_get_regname(offset), + (unsigned int)offset, v); + + switch (offset) { + case IADR_ADDR: + s->iadr = v & IADR_MASK; + //i2c_set_slave_address(s->bus, (uint8_t)s->iadr); + break; + case IFDR_ADDR: + s->ifdr = v & IFDR_MASK; + break; + case I2CR_ADDR: + if (imx_i2c_is_enabled(s) && ((v & I2CR_IEN) == 0)) { + /* This is a soft reset. IADR is preserved during soft resets */ + uint16_t iadr = s->iadr; + imx_i2c_reset(&s->busdev.qdev); + s->iadr = iadr; + } else { // normal write + s->i2cr = v & I2CR_MASK; + + if (imx_i2c_is_master(s)) { // master mode + // set the bus to busy + s->i2sr |= I2SR_IBB; + } else { // slave mode + // bus is not busy anymore + s->i2sr &= ~I2SR_IBB; + + // if we unset the master mode then it ends the ongoing + // transfer if any + if (s->address != ADDR_RESET) { + i2c_end_transfer(s->bus); + s->address = ADDR_RESET; + } + } + + if (s->i2cr & I2CR_RSTA) { // Restart + // if this is a restart then it ends the ongoing transfer + if (s->address != ADDR_RESET) { + i2c_end_transfer(s->bus); + s->address = ADDR_RESET; + s->i2cr &= ~I2CR_RSTA; + } + } + } + break; + case I2SR_ADDR: + /* + * if the user writes 0 to IIF then lower the interrupt and + * reset the bit + */ + if ((s->i2sr & I2SR_IIF) && !(v & I2SR_IIF)) { + s->i2sr &= ~I2SR_IIF; + qemu_irq_lower(s->irq); + } + + /* + * if the user writes 0 to IAL, reset the bit + */ + if ((s->i2sr & I2SR_IAL) && !(v & I2SR_IAL)) { + s->i2sr &= ~I2SR_IAL; + /* Nothing more to do ? */ + } + + break; + case I2DR_ADDR: + /* if the device is not enabled, nothing to do */ + if (!imx_i2c_is_enabled(s)) { + break; + } + + s->i2dr_write = v & I2DR_MASK; + + if (imx_i2c_is_master(s)) { // master mode + /* If this is the first write cycle then it is the slave addr */ + if (s->address == ADDR_RESET) { + if (!i2c_start_transfer(s->bus, (uint8_t)s->i2dr_write >> 1, + (int)s->i2dr_write & 0x01)) { + // if 0 is returned, the adress is valid + s->address = s->i2dr_write; + s->i2sr &= ~I2SR_RXAK; + imx_i2c_raise_interrupt(s); + } else { // can't start i2c transaction + } + } else { // This is a normal data write + if (i2c_send(s->bus, s->i2dr_write)) { + // if the target return non zero then end the transfer + i2c_end_transfer(s->bus); + } + s->i2sr &= ~I2SR_RXAK; + imx_i2c_raise_interrupt(s); + } + } else { // slave mode + } + break; + default: + hw_error("%s: Bad address 0x%x\n", __func__, (int)offset); + break; + } +} + +static const MemoryRegionOps imx_i2c_ops = { + .read = imx_i2c_read, + .write = imx_i2c_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static const VMStateDescription imx_i2c_vmstate = { + .name = TYPE_IMX_I2C, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT16(address, imx_i2c_state), + VMSTATE_UINT16(iadr, imx_i2c_state), + VMSTATE_UINT16(ifdr, imx_i2c_state), + VMSTATE_UINT16(i2cr, imx_i2c_state), + VMSTATE_UINT16(i2sr, imx_i2c_state), + VMSTATE_UINT16(i2dr_read, imx_i2c_state), + VMSTATE_UINT16(i2dr_write, imx_i2c_state), + VMSTATE_END_OF_LIST() + } +}; + +static int imx_i2c_init(SysBusDevice *dev) +{ + imx_i2c_state *s = IMX_I2C(dev); + + memory_region_init_io(&s->iomem, &imx_i2c_ops, s, TYPE_IMX_I2C, + IMX_I2C_MEM_SIZE); + sysbus_init_mmio(dev, &s->iomem); + sysbus_init_irq(dev, &s->irq); + s->bus = i2c_init_bus(&dev->qdev, "i2c"); + + return 0; +} + +static void imx_i2c_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *sbdc = SYS_BUS_DEVICE_CLASS(klass); + + dc->vmsd = &imx_i2c_vmstate; + dc->reset = imx_i2c_reset; + sbdc->init = imx_i2c_init; +} + +static const TypeInfo imx_i2c_type_info = { + .name = TYPE_IMX_I2C, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(imx_i2c_state), + .class_init = imx_i2c_class_init, +}; + +static void imx_i2c_register_types(void) +{ + type_register_static(&imx_i2c_type_info); +} + +type_init(imx_i2c_register_types);