[AArch64] Fix for LDR/STR to/from S and D registers

Submitted by Ian Bolton on May 1, 2013, 6:41 p.m.


Message ID 000501ce469b$81cffd90$856ff8b0$@bolton@arm.com
State New
Headers show

Commit Message

Ian Bolton May 1, 2013, 6:41 p.m.
This is a fix for this patch:

If someone compiles with -mgeneral-regs-only then those instructions
shouldn't be used. We can enforce that by adding the fp attribute to
the relevant alternatives in the patterns.

Regression tests all good.

OK for trunk?


2013-05-01  Ian Bolton  <ian.bolton@arm.com>

* config/aarch64/aarch64.md (movsi_aarch64): Only allow to/from
S reg when fp attribute set.
(movdi_aarch64): Only allow to/from D reg when fp attribute set.

Patch hide | download patch | download mbox

Index: gcc/config/aarch64/aarch64.md
--- gcc/config/aarch64/aarch64.md	(revision 198456)
+++ gcc/config/aarch64/aarch64.md	(working copy)
@@ -825,7 +825,7 @@  (define_insn "*movsi_aarch64"
    fmov\\t%s0, %s1"
   [(set_attr "v8type" "move,alu,load1,load1,store1,store1,fmov,fmov,fmov")
    (set_attr "mode" "SI")
-   (set_attr "fp" "*,*,*,*,*,*,yes,yes,yes")]
+   (set_attr "fp" "*,*,*,yes,*,yes,yes,yes,yes")]
 (define_insn "*movdi_aarch64"
@@ -850,7 +850,7 @@  (define_insn "*movdi_aarch64"
    movi\\t%d0, %1"
   [(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov,fmov")
    (set_attr "mode" "DI")
-   (set_attr "fp" "*,*,*,*,*,*,*,*,*,*,yes,yes,yes,yes")]
+   (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,yes")]
 (define_insn "insv_imm<mode>"