From patchwork Tue Apr 30 15:08:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Greenhalgh X-Patchwork-Id: 240640 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 173F42C00B1 for ; Wed, 1 May 2013 01:08:24 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=y8IHcvRJxX+qJWWhSYfJ3qzpQDcCNltvOGgOzgmo/CjH2pzMuG dzrf+ybL0KyEwuY93HgOCVjQV8zqoz17pPuxlJFA4xIkoxc98zVuF1eaq1qUyPhs WTtkIuMcAP6hR+DN7TJ4k7QodvQ45/BVz91vWs0hpokqaKgs028IPtlpQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=DjzZqLS8bkHXY61kx7DdALgeGHQ=; b=wjeAAAeOCMvnaC/AzuLK y+eJrGhpG+fMgZMLLQpdjcb31zGdiZVUPCg37jShK/JgF/oHRJrbf2pG9zVaAoUZ bazpAz2JNuhpYqxTV2kQ6lOobzpIr1avVxMVXA3Ul58TAeen4Rjo2PeJhFDX/j3q X9U2/Sp6fAWvf6eMB5R/ke0= Received: (qmail 30535 invoked by alias); 30 Apr 2013 15:08:17 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 30522 invoked by uid 89); 30 Apr 2013 15:08:17 -0000 X-Spam-SWARE-Status: No, score=-4.6 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_HOSTKARMA_W, RCVD_IN_HOSTKARMA_WL, SPF_PASS, TW_EQ, TW_QZ, TW_VC autolearn=ham version=3.3.1 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Tue, 30 Apr 2013 15:08:16 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 30 Apr 2013 16:08:13 +0100 Received: from e106375-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Tue, 30 Apr 2013 16:08:13 +0100 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: marcus.shawcroft@arm.com Subject: [AArch64 Testsuite] Fix fallout from FCM changes. Date: Tue, 30 Apr 2013 16:08:07 +0100 Message-Id: <1367334487-22775-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: 113043016081315201 X-Virus-Found: No Hi, gcc.target/aarch64/scalar_intrinsics.c uses the vcled_s64 style intrinsics. As these now just map to a C operation, we need to first ensure that the arguments to these functions make their way to the SIMD register set. For the >= 0 and < 0 opertaions idiom recognition will convert them to shifts, so we also need to mop up the expectations on numbers of shifts and generation of cmge d0, d0, #0. Tested to ensure test still passes. Thanks, James --- gcc/testsuite/ 2013-04-30 James Greenhalgh * gcc.target/aarch64/scalar_intrinsics.c (force_simd): New. (test_vceqd_s64): Force arguments to SIMD registers. (test_vceqzd_s64): Likewise. (test_vcged_s64): Likewise. (test_vcled_s64): Likewise. (test_vcgezd_s64): Likewise. (test_vcged_u64): Likewise. (test_vcgtd_s64): Likewise. (test_vcltd_s64): Likewise. (test_vcgtzd_s64): Likewise. (test_vcgtd_u64): Likewise. (test_vclezd_s64): Likewise. (test_vcltzd_s64): Likewise. (test_vtst_s64): Likewise. (test_vtst_u64): Likewise. diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c index 1b85308..e984b8e 100644 --- a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c +++ b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c @@ -1,7 +1,13 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -#include "../../../config/aarch64/arm_neon.h" +#include + +/* Used to force a variable to a SIMD register. */ +#define force_simd(V1) asm volatile ("mov %d0, %d1" \ + : "=w"(V1) \ + : "w"(V1) \ + : /* No clobbers */); /* { dg-final { scan-assembler-times "\\tadd\\tx\[0-9\]+" 2 } } */ @@ -31,7 +37,12 @@ test_vaddd_s64_2 (int64x1_t a, int64x1_t b, int64x1_t c, int64x1_t d) uint64x1_t test_vceqd_s64 (int64x1_t a, int64x1_t b) { - return vceqd_s64 (a, b); + uint64x1_t res; + force_simd (a); + force_simd (b); + res = vceqd_s64 (a, b); + force_simd (res); + return res; } /* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ @@ -39,7 +50,11 @@ test_vceqd_s64 (int64x1_t a, int64x1_t b) uint64x1_t test_vceqzd_s64 (int64x1_t a) { - return vceqzd_s64 (a); + uint64x1_t res; + force_simd (a); + res = vceqzd_s64 (a); + force_simd (res); + return res; } /* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */ @@ -47,21 +62,36 @@ test_vceqzd_s64 (int64x1_t a) uint64x1_t test_vcged_s64 (int64x1_t a, int64x1_t b) { - return vcged_s64 (a, b); + uint64x1_t res; + force_simd (a); + force_simd (b); + res = vcged_s64 (a, b); + force_simd (res); + return res; } uint64x1_t test_vcled_s64 (int64x1_t a, int64x1_t b) { - return vcled_s64 (a, b); + uint64x1_t res; + force_simd (a); + force_simd (b); + res = vcled_s64 (a, b); + force_simd (res); + return res; } -/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ +/* Idiom recognition will cause this testcase not to generate + the expected cmge instruction, so do not check for it. */ uint64x1_t test_vcgezd_s64 (int64x1_t a) { - return vcgezd_s64 (a); + uint64x1_t res; + force_simd (a); + res = vcgezd_s64 (a); + force_simd (res); + return res; } /* { dg-final { scan-assembler-times "\\tcmhs\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ @@ -69,7 +99,12 @@ test_vcgezd_s64 (int64x1_t a) uint64x1_t test_vcged_u64 (uint64x1_t a, uint64x1_t b) { - return vcged_u64 (a, b); + uint64x1_t res; + force_simd (a); + force_simd (b); + res = vcged_u64 (a, b); + force_simd (res); + return res; } /* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */ @@ -77,13 +112,23 @@ test_vcged_u64 (uint64x1_t a, uint64x1_t b) uint64x1_t test_vcgtd_s64 (int64x1_t a, int64x1_t b) { - return vcgtd_s64 (a, b); + uint64x1_t res; + force_simd (a); + force_simd (b); + res = vcgtd_s64 (a, b); + force_simd (res); + return res; } uint64x1_t test_vcltd_s64 (int64x1_t a, int64x1_t b) { - return vcltd_s64 (a, b); + uint64x1_t res; + force_simd (a); + force_simd (b); + res = vcltd_s64 (a, b); + force_simd (res); + return res; } /* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ @@ -91,7 +136,11 @@ test_vcltd_s64 (int64x1_t a, int64x1_t b) uint64x1_t test_vcgtzd_s64 (int64x1_t a) { - return vcgtzd_s64 (a); + uint64x1_t res; + force_simd (a); + res = vcgtzd_s64 (a); + force_simd (res); + return res; } /* { dg-final { scan-assembler-times "\\tcmhi\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */ @@ -99,7 +148,12 @@ test_vcgtzd_s64 (int64x1_t a) uint64x1_t test_vcgtd_u64 (uint64x1_t a, uint64x1_t b) { - return vcgtd_u64 (a, b); + uint64x1_t res; + force_simd (a); + force_simd (b); + res = vcgtd_u64 (a, b); + force_simd (res); + return res; } /* { dg-final { scan-assembler-times "\\tcmle\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ @@ -107,15 +161,24 @@ test_vcgtd_u64 (uint64x1_t a, uint64x1_t b) uint64x1_t test_vclezd_s64 (int64x1_t a) { - return vclezd_s64 (a); + uint64x1_t res; + force_simd (a); + res = vclezd_s64 (a); + force_simd (res); + return res; } -/* { dg-final { scan-assembler-times "\\tcmlt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */ +/* Idiom recognition will cause this testcase not to generate + the expected cmlt instruction, so do not check for it. */ uint64x1_t test_vcltzd_s64 (int64x1_t a) { - return vcltzd_s64 (a); + uint64x1_t res; + force_simd (a); + res = vcltzd_s64 (a); + force_simd (res); + return res; } /* { dg-final { scan-assembler-times "\\tdup\\tb\[0-9\]+, v\[0-9\]+\.b" 2 } } */ @@ -179,13 +242,23 @@ test_vdupd_lane_u64 (uint64x2_t a) int64x1_t test_vtst_s64 (int64x1_t a, int64x1_t b) { - return vtstd_s64 (a, b); + uint64x1_t res; + force_simd (a); + force_simd (b); + res = vtstd_s64 (a, b); + force_simd (res); + return res; } uint64x1_t test_vtst_u64 (uint64x1_t a, uint64x1_t b) { - return vtstd_u64 (a, b); + uint64x1_t res; + force_simd (a); + force_simd (b); + res = vtstd_s64 (a, b); + force_simd (res); + return res; } /* { dg-final { scan-assembler-times "\\taddp\\td\[0-9\]+, v\[0-9\]+\.2d" 1 } } */ @@ -722,7 +795,10 @@ test_vrshld_u64 (uint64x1_t a, uint64x1_t b) return vrshld_u64 (a, b); } -/* { dg-final { scan-assembler-times "\\tasr\\tx\[0-9\]+" 1 } } */ +/* Other intrinsics can generate an asr instruction (vcltzd, vcgezd), + so we cannot check scan-assembler-times. */ + +/* { dg-final { scan-assembler "\\tasr\\tx\[0-9\]+" } } */ int64x1_t test_vshrd_n_s64 (int64x1_t a)