From patchwork Sat Apr 27 07:12:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artyom Tarasenko X-Patchwork-Id: 240090 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 96E3F2C0106 for ; Sat, 27 Apr 2013 17:13:02 +1000 (EST) Received: from localhost ([::1]:36192 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UVzJc-0006RE-NS for incoming@patchwork.ozlabs.org; Sat, 27 Apr 2013 03:13:00 -0400 Received: from eggs.gnu.org ([208.118.235.92]:37005) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UVzJA-0006NB-0j for qemu-devel@nongnu.org; Sat, 27 Apr 2013 03:12:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UVzJ8-0004Lm-NR for qemu-devel@nongnu.org; Sat, 27 Apr 2013 03:12:31 -0400 Received: from mail-bk0-x22e.google.com ([2a00:1450:4008:c01::22e]:34198) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UVzJ8-0004Le-GM for qemu-devel@nongnu.org; Sat, 27 Apr 2013 03:12:30 -0400 Received: by mail-bk0-f46.google.com with SMTP id e19so1603078bku.19 for ; Sat, 27 Apr 2013 00:12:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:in-reply-to:references; bh=xuMsff599pgoqAWhd+cnaeKZWZP8G9spJ+85wguUcuQ=; b=HIJJiGyXihgUoDZezL+UQ1GfkRwni7l0BgIftMjoL+keO0EXUt98FON+YE9lvjXrZo /1b3iQzPoxFcx9yc68d994vL3nDrDUbglcpWqVUv7sU9HzkvKugsF5j2dFl1YhvijDd/ PWW2Jwqc+nWKStoPHP6/3KZQPKrW4ZwCgs+gBio+dhBL68btMycb0A9EAfnQTBkznVnS dCfhoUmwc0USCbQ0Adl/MgCqdca955oGYcoFlR1lKwkv6J3xXGyHx+f0WQ9pdwpNz+hw QvIMNSXnQ4UBLOyEndjTxeHa2wAOw6niRkG/Qw44Dj+PH5xpPkkoMjC2E9Nw18CQ+iuh FWUQ== X-Received: by 10.205.108.72 with SMTP id eb8mr19522868bkc.111.1367046749725; Sat, 27 Apr 2013 00:12:29 -0700 (PDT) Received: from localhost (e181210163.adsl.alicedsl.de. [85.181.210.163]) by mx.google.com with ESMTPSA id fh8sm4070445bkc.10.2013.04.27.00.12.28 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Sat, 27 Apr 2013 00:12:29 -0700 (PDT) From: Artyom Tarasenko To: qemu-devel@nongnu.org Date: Sat, 27 Apr 2013 09:12:17 +0200 Message-Id: X-Mailer: git-send-email 1.7.1 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:4008:c01::22e Cc: blauwirbel@gmail.com, Artyom Tarasenko Subject: [Qemu-devel] [PATCH 1/2] m48t59: use mmio for the m48t08 model of the m48t59_isa card X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org PrEP and SPARC machines use slightly different variations of a Mostek NVRAM chip. Since the SPARC variant is much closer to a m48t08 type, the model can be used to differentiate between the PIO and MMIO accesses. Signed-off-by: Artyom Tarasenko --- hw/timer/m48t59.c | 38 +++++++++++++++++++++++++++++++++++--- 1 files changed, 35 insertions(+), 3 deletions(-) diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c index 5019e06..00ad417 100644 --- a/hw/timer/m48t59.c +++ b/hw/timer/m48t59.c @@ -632,6 +632,33 @@ static const MemoryRegionOps m48t59_io_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; +static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned size) +{ + M48t59State *NVRAM = opaque; + uint32_t retval; + + retval = m48t59_read(NVRAM, addr); + return retval; +} + +static void nvram_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + M48t59State *NVRAM = opaque; + + m48t59_write(NVRAM, addr, value & 0xff); +} + +static const MemoryRegionOps m48t59_mmio_ops = { + .read = nvram_read, + .write = nvram_write, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + /* Initialisation routine */ M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base, uint32_t io_base, uint16_t size, int model) @@ -676,7 +703,11 @@ M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, d = DO_UPCAST(M48t59ISAState, busdev, dev); s = &d->state; - memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4); + if (model == 59) { + memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4); + } else { + memory_region_init_io(&d->io, &m48t59_mmio_ops, s, "m48t59", size); + } if (io_base != 0) { isa_register_ioport(dev, &d->io, io_base); } @@ -700,8 +731,9 @@ static int m48t59_init_isa1(ISADevice *dev) { M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev); M48t59State *s = &d->state; - - isa_init_irq(dev, &s->IRQ, 8); + if (s->model == 59) { + isa_init_irq(dev, &s->IRQ, 8); + } m48t59_init_common(s); return 0;