From patchwork Sat Apr 27 05:55:12 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Artyom Tarasenko X-Patchwork-Id: 240078 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A2E142C00E9 for ; Sat, 27 Apr 2013 15:56:01 +1000 (EST) Received: from localhost ([::1]:40722 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UVy75-0003Lb-Uo for incoming@patchwork.ozlabs.org; Sat, 27 Apr 2013 01:55:59 -0400 Received: from eggs.gnu.org ([208.118.235.92]:53449) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UVy6X-0003HY-Dm for qemu-devel@nongnu.org; Sat, 27 Apr 2013 01:55:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UVy6V-0008LO-QU for qemu-devel@nongnu.org; Sat, 27 Apr 2013 01:55:25 -0400 Received: from mail-bk0-x22b.google.com ([2a00:1450:4008:c01::22b]:44659) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UVy6V-0008L8-FV for qemu-devel@nongnu.org; Sat, 27 Apr 2013 01:55:23 -0400 Received: by mail-bk0-f43.google.com with SMTP id jm19so2026329bkc.2 for ; Fri, 26 Apr 2013 22:55:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:in-reply-to:references:mime-version:content-type :content-transfer-encoding; bh=4SeEjO1TLx4toIC1EnzAycAUbsPftw6HUBGcH3gupbo=; b=sJ3bphetDDuqc8Dhf1Fo8R4+L0qNQtUnTceV9bMhZRYzgpqBOhP1oRhod7m6Ryp29w hDMerkp+zsMUA2UpbzCouKx/yqzhDJiRqB4bgspQqeEddm1t3heQ9ekXiUEn843+xtQa M0UY3gGm/6qj8Ygk+ehObgiHQv7wP53ST933poObgGB2TkaXyu4MkltMNcdkzwkUPGwE nV/dUzo6bKtNFMJHWZZBMVVRED9ckXwq2K1l1RzNHZo42uWlI9zRVoy/1vbFMQcjLh4N IZJ8jK68f3d8ZSJtYPFW3SjOleU6N8LiUuI++Tdhe8K9YovxkJLqGer9AiRq5Kh6SHbj xQZw== X-Received: by 10.204.225.16 with SMTP id iq16mr19264544bkb.35.1367042122480; Fri, 26 Apr 2013 22:55:22 -0700 (PDT) Received: from localhost (e181210163.adsl.alicedsl.de. [85.181.210.163]) by mx.google.com with ESMTPSA id cv9sm4040204bkb.5.2013.04.26.22.55.21 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Fri, 26 Apr 2013 22:55:22 -0700 (PDT) From: Artyom Tarasenko To: qemu-devel@nongnu.org Date: Sat, 27 Apr 2013 07:55:12 +0200 Message-Id: X-Mailer: git-send-email 1.7.1 In-Reply-To: References: In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:4008:c01::22b Cc: blauwirbel@gmail.com, Artyom Tarasenko Subject: [Qemu-devel] [PATCH 2/3] sparc64: fix loosing interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org - clear interrupts only on writing to the interrupt clear registers - don't overwrite a currently active interrupt request - use the correct addresses for the interrupt clear registers (section 19.3.3.3 of the UltraSPARC™-IIi User’s Manual) Signed-off-by: Artyom Tarasenko --- hw/pci-host/apb.c | 114 ++++++++++++++++++++++++++++++++++++++++++++-------- 1 files changed, 96 insertions(+), 18 deletions(-) diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 3bc0d10..356853a 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -2,6 +2,7 @@ * QEMU Ultrasparc APB PCI host * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2012,2013 Artyom Tarasenko * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -67,6 +68,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) #define RESET_WMASK 0x60000000 #define MAX_IVEC 0x40 +#define NO_IRQ_REQUEST (MAX_IVEC + 1) typedef struct APBState { SysBusDevice busdev; @@ -75,17 +77,64 @@ typedef struct APBState { MemoryRegion pci_config; MemoryRegion pci_mmio; MemoryRegion pci_ioport; + uint64_t pci_irq_in; uint32_t iommu[4]; uint32_t pci_control[16]; uint32_t pci_irq_map[8]; uint32_t obio_irq_map[32]; qemu_irq *pbm_irqs; qemu_irq *ivec_irqs; + unsigned int irq_request; uint32_t reset_control; unsigned int nr_resets; } APBState; -static void pci_apb_set_irq(void *opaque, int irq_num, int level); +static inline void pbm_set_request(APBState *s, unsigned int irq_num) +{ + APB_DPRINTF("%s: request irq %d\n", __func__, irq_num); + + s->irq_request = irq_num; + qemu_set_irq(s->ivec_irqs[irq_num], 1); +} + +static inline void pbm_check_irqs(APBState *s) +{ + + unsigned int i; + + /* Previous request is not acknowledged, resubmit */ + if (s->irq_request != NO_IRQ_REQUEST) { + pbm_set_request(s, s->irq_request); + return; + } + /* no request pending */ + if (s->pci_irq_in == 0ULL) { + return; + } + for (i = 0; i < 32; i++) { + if (s->pci_irq_in & (1ULL << i)) { + if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) { + pbm_set_request(s, i); + return; + } + } + } + for (i = 32; i < 64; i++) { + if (s->pci_irq_in & (1ULL << i)) { + if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) { + pbm_set_request(s, i); + break; + } + } + } +} + +static inline void pbm_clear_request(APBState *s, unsigned int irq_num) +{ + APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num); + qemu_set_irq(s->ivec_irqs[irq_num], 0); + s->irq_request = NO_IRQ_REQUEST; +} static void apb_config_writel (void *opaque, hwaddr addr, uint64_t val, unsigned size) @@ -105,24 +154,43 @@ static void apb_config_writel (void *opaque, hwaddr addr, break; case 0xc00 ... 0xc3f: /* PCI interrupt control */ if (addr & 4) { - s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK; - s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK; + unsigned int ino = (addr & 0x3f) >> 3; + s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK; + s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; + if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) { + pbm_clear_request(s, ino); + } + pbm_check_irqs(s); } break; case 0x1000 ... 0x1080: /* OBIO interrupt control */ if (addr & 4) { - s->obio_irq_map[(addr & 0xff) >> 3] &= PBM_PCI_IMR_MASK; - s->obio_irq_map[(addr & 0xff) >> 3] |= val & ~PBM_PCI_IMR_MASK; + unsigned int ino = ((addr & 0xff) >> 3); + s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK; + s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; + if ((s->irq_request == (ino | 0x20)) + && !(val & ~PBM_PCI_IMR_MASK)) { + pbm_clear_request(s, ino | 0x20); + } + pbm_check_irqs(s); } break; - case 0x1400 ... 0x143f: /* PCI interrupt clear */ + case 0x1400 ... 0x14ff: /* PCI interrupt clear */ if (addr & 4) { - pci_apb_set_irq(s, (addr & 0x3f) >> 3, 0); + unsigned int ino = (addr & 0xff) >> 5; + if ((s->irq_request / 4) == ino) { + pbm_clear_request(s, s->irq_request); + pbm_check_irqs(s); + } } break; case 0x1800 ... 0x1860: /* OBIO interrupt clear */ if (addr & 4) { - pci_apb_set_irq(s, 0x20 | ((addr & 0xff) >> 3), 0); + unsigned int ino = ((addr & 0xff) >> 3) | 0x20; + if (s->irq_request == ino) { + pbm_clear_request(s, ino); + pbm_check_irqs(s); + } } break; case 0x2000 ... 0x202f: /* PCI control */ @@ -304,23 +372,28 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level) { APBState *s = opaque; + APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level); /* PCI IRQ map onto the first 32 INO. */ if (irq_num < 32) { - if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) { - APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level); - qemu_set_irq(s->ivec_irqs[irq_num], level); + if (level) { + s->pci_irq_in |= 1ULL << irq_num; + if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) { + pbm_set_request(s, irq_num); + } } else { - APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num); - qemu_irq_lower(s->ivec_irqs[irq_num]); + s->pci_irq_in &= ~(1ULL << irq_num); } } else { - /* OBIO IRQ map onto the next 16 INO. */ - if (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED) { + /* OBIO IRQ map onto the next 32 INO. */ + if (level) { APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level); - qemu_set_irq(s->ivec_irqs[irq_num], level); + s->pci_irq_in |= 1ULL << irq_num; + if ((s->irq_request == NO_IRQ_REQUEST) + && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) { + pbm_set_request(s, irq_num); + } } else { - APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num); - qemu_irq_lower(s->ivec_irqs[irq_num]); + s->pci_irq_in &= ~(1ULL << irq_num); } } } @@ -420,6 +493,9 @@ static void pci_pbm_reset(DeviceState *d) s->obio_irq_map[i] &= PBM_PCI_IMR_MASK; } + s->irq_request = NO_IRQ_REQUEST; + s->pci_irq_in = 0ULL; + if (s->nr_resets++ == 0) { /* Power on reset */ s->reset_control = POR; @@ -445,6 +521,8 @@ static int pci_pbm_init_device(SysBusDevice *dev) s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i; } s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC); + s->irq_request = NO_IRQ_REQUEST; + s->pci_irq_in = 0ULL; /* apb_config */ memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config",