Patchwork ppc/spapr: Fix cache related properties

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Submitter Benjamin Herrenschmidt
Date April 26, 2013, 9:21 p.m.
Message ID <1367011280.17497.24.camel@pasglop>
Download mbox | patch
Permalink /patch/240050/
State New
Headers show

Comments

Benjamin Herrenschmidt - April 26, 2013, 9:21 p.m.
The properties in the CPU nodes for expressing the cache block size
are spelled {d,i}-cache... not {d,i}cache...

Also add the "line" variants in addition to the "block" variants for
completeness (some OSes might require them).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
Alexander Graf - May 2, 2013, 11:10 a.m.
On 26.04.2013, at 23:21, Benjamin Herrenschmidt wrote:

> The properties in the CPU nodes for expressing the cache block size
> are spelled {d,i}-cache... not {d,i}cache...
> 
> Also add the "line" variants in addition to the "block" variants for
> completeness (some OSes might require them).
> 
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

This patch is (in a modified, extended form) already in the tree:

commit 0cbad81f70546b58f08de3225f1eca7a8b869b09
Author: David Gibson <david@gibson.dropbear.id.au>
Date:   Sun Apr 7 19:08:19 2013 +0000

    pseries: Fixes and enhancements to L1 cache properties

    PAPR requires that the device tree's CPU nodes have several properties
    with information about the L1 cache.  We already create two of these
    properties, but with incorrect names - "[id]cache-block-size" instead
    of "[id]-cache-block-size" (note the extra hyphen).

    We were also missing some of the required cache properties.  This
    patch adds the [id]-cache-line-size properties (which have the same
    values as the block size properties in all current cases).  We also
    add the [id]-cache-size properties.

    Adding the cache sizes requires some extra infrastructure in the
    general target-ppc code to (optionally) set the cache sizes for
    various CPUs.  The CPU family descriptions in translate_init.c can set
    these sizes - this patch adds correct information for POWER7, I'm
    leaving other CPU types to people who have a physical example to
    verify against.  In addition, for -cpu host we take the values
    advertised by the host (if available) and use those to override the
    information based on PVR.

    Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
    Signed-off-by: Alexander Graf <agraf@suse.de>



Alex

> ---
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 7a42501..7582a05 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -333,9 +333,13 @@ static void *spapr_create_fdt_skel(const char *cpu_model,
>         _FDT((fdt_property_string(fdt, "device_type", "cpu")));
> 
>         _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
> -        _FDT((fdt_property_cell(fdt, "dcache-block-size",
> +        _FDT((fdt_property_cell(fdt, "d-cache-block-size",
>                                 env->dcache_line_size)));
> -        _FDT((fdt_property_cell(fdt, "icache-block-size",
> +        _FDT((fdt_property_cell(fdt, "i-cache-block-size",
> +                                env->icache_line_size)));
> +        _FDT((fdt_property_cell(fdt, "d-cache-line-size",
> +                                env->dcache_line_size)));
> +        _FDT((fdt_property_cell(fdt, "i-cache-line-size",
>                                 env->icache_line_size)));
>         _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
>         _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
> 
> 
>
Benjamin Herrenschmidt - May 2, 2013, 11:25 a.m.
On Thu, 2013-05-02 at 13:10 +0200, Alexander Graf wrote:
> This patch is (in a modified, extended form) already in the tree:

Ah yes, it wasn't upstream when I started hacking on that stuff and
so I missed it. Just drop mine.

Cheers,
Ben.

Patch

diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 7a42501..7582a05 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -333,9 +333,13 @@  static void *spapr_create_fdt_skel(const char *cpu_model,
         _FDT((fdt_property_string(fdt, "device_type", "cpu")));
 
         _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
-        _FDT((fdt_property_cell(fdt, "dcache-block-size",
+        _FDT((fdt_property_cell(fdt, "d-cache-block-size",
                                 env->dcache_line_size)));
-        _FDT((fdt_property_cell(fdt, "icache-block-size",
+        _FDT((fdt_property_cell(fdt, "i-cache-block-size",
+                                env->icache_line_size)));
+        _FDT((fdt_property_cell(fdt, "d-cache-line-size",
+                                env->dcache_line_size)));
+        _FDT((fdt_property_cell(fdt, "i-cache-line-size",
                                 env->icache_line_size)));
         _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
         _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));