From patchwork Fri Apr 26 18:30:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 239918 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id A2DDF2C0121 for ; Sat, 27 Apr 2013 04:30:57 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757311Ab3DZSax (ORCPT ); Fri, 26 Apr 2013 14:30:53 -0400 Received: from cantor2.suse.de ([195.135.220.15]:39455 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757284Ab3DZSat (ORCPT ); Fri, 26 Apr 2013 14:30:49 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 4A5DA5E000232; Fri, 26 Apr 2013 20:30:39 +0200 (CEST) From: Alexander Graf To: kvm-ppc@vger.kernel.org Cc: "kvm@vger.kernel.org mailing list" , Marcelo Tosatti , Gleb Natapov , Scott Wood Subject: [PATCH 27/42] kvm/ppc/mpic: adapt to kernel style and environment Date: Fri, 26 Apr 2013 20:30:22 +0200 Message-Id: <1367001037-10394-49-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1367001037-10394-1-git-send-email-agraf@suse.de> References: <1367001037-10394-1-git-send-email-agraf@suse.de> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Scott Wood Remove braces that Linux style doesn't permit, remove space after '*' that Lindent added, keep error/debug strings contiguous, etc. Substitute type names, debug prints, etc. Signed-off-by: Scott Wood Signed-off-by: Alexander Graf --- arch/powerpc/kvm/mpic.c | 445 ++++++++++++++++++++++------------------------- 1 files changed, 208 insertions(+), 237 deletions(-) diff --git a/arch/powerpc/kvm/mpic.c b/arch/powerpc/kvm/mpic.c index d6d70a4..1df67ae 100644 --- a/arch/powerpc/kvm/mpic.c +++ b/arch/powerpc/kvm/mpic.c @@ -42,22 +42,22 @@ #define OPENPIC_TMR_REG_SIZE 0x220 #define OPENPIC_MSI_REG_START 0x1600 #define OPENPIC_MSI_REG_SIZE 0x200 -#define OPENPIC_SUMMARY_REG_START 0x3800 -#define OPENPIC_SUMMARY_REG_SIZE 0x800 +#define OPENPIC_SUMMARY_REG_START 0x3800 +#define OPENPIC_SUMMARY_REG_SIZE 0x800 #define OPENPIC_SRC_REG_START 0x10000 #define OPENPIC_SRC_REG_SIZE (MAX_SRC * 0x20) #define OPENPIC_CPU_REG_START 0x20000 -#define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) +#define OPENPIC_CPU_REG_SIZE (0x100 + ((MAX_CPU - 1) * 0x1000)) -typedef struct FslMpicInfo { +struct fsl_mpic_info { int max_ext; -} FslMpicInfo; +}; -static FslMpicInfo fsl_mpic_20 = { +static struct fsl_mpic_info fsl_mpic_20 = { .max_ext = 12, }; -static FslMpicInfo fsl_mpic_42 = { +static struct fsl_mpic_info fsl_mpic_42 = { .max_ext = 12, }; @@ -100,44 +100,43 @@ static int get_current_cpu(void) { CPUState *cpu_single_cpu; - if (!cpu_single_env) { + if (!cpu_single_env) return -1; - } cpu_single_cpu = ENV_GET_CPU(cpu_single_env); return cpu_single_cpu->cpu_index; } -static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, int idx); -static void openpic_cpu_write_internal(void *opaque, hwaddr addr, +static uint32_t openpic_cpu_read_internal(void *opaque, gpa_t addr, int idx); +static void openpic_cpu_write_internal(void *opaque, gpa_t addr, uint32_t val, int idx); -typedef enum IRQType { +enum irq_type { IRQ_TYPE_NORMAL = 0, IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */ IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */ -} IRQType; +}; -typedef struct IRQQueue { +struct irq_queue { /* Round up to the nearest 64 IRQs so that the queue length * won't change when moving between 32 and 64 bit hosts. */ unsigned long queue[BITS_TO_LONGS((MAX_IRQ + 63) & ~63)]; int next; int priority; -} IRQQueue; +}; -typedef struct IRQSource { +struct irq_source { uint32_t ivpr; /* IRQ vector/priority register */ uint32_t idr; /* IRQ destination register */ uint32_t destmask; /* bitmap of CPU destinations */ int last_cpu; int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */ int pending; /* TRUE if IRQ is pending */ - IRQType type; + enum irq_type type; bool level:1; /* level-triggered */ - bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */ -} IRQSource; + bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */ +}; #define IVPR_MASK_SHIFT 31 #define IVPR_MASK_MASK (1 << IVPR_MASK_SHIFT) @@ -158,22 +157,19 @@ typedef struct IRQSource { #define IDR_EP 0x80000000 /* external pin */ #define IDR_CI 0x40000000 /* critical interrupt */ -typedef struct IRQDest { +struct irq_dest { int32_t ctpr; /* CPU current task priority */ - IRQQueue raised; - IRQQueue servicing; + struct irq_queue raised; + struct irq_queue servicing; qemu_irq *irqs; /* Count of IRQ sources asserting on non-INT outputs */ uint32_t outputs_active[OPENPIC_OUTPUT_NB]; -} IRQDest; - -typedef struct OpenPICState { - SysBusDevice busdev; - MemoryRegion mem; +}; +struct openpic { /* Behavior control */ - FslMpicInfo *fsl; + struct fsl_mpic_info *fsl; uint32_t model; uint32_t flags; uint32_t nb_irqs; @@ -186,9 +182,6 @@ typedef struct OpenPICState { uint32_t brr1; uint32_t mpic_mode_mask; - /* Sub-regions */ - MemoryRegion sub_io_mem[6]; - /* Global registers */ uint32_t frr; /* Feature reporting register */ uint32_t gcr; /* Global configuration register */ @@ -196,9 +189,9 @@ typedef struct OpenPICState { uint32_t spve; /* Spurious vector register */ uint32_t tfrr; /* Timer frequency reporting register */ /* Source registers */ - IRQSource src[MAX_IRQ]; + struct irq_source src[MAX_IRQ]; /* Local registers per output pin */ - IRQDest dst[MAX_CPU]; + struct irq_dest dst[MAX_CPU]; uint32_t nb_cpus; /* Timer registers */ struct { @@ -213,24 +206,24 @@ typedef struct OpenPICState { uint32_t irq_ipi0; uint32_t irq_tim0; uint32_t irq_msi; -} OpenPICState; +}; -static inline void IRQ_setbit(IRQQueue * q, int n_IRQ) +static inline void IRQ_setbit(struct irq_queue *q, int n_IRQ) { set_bit(n_IRQ, q->queue); } -static inline void IRQ_resetbit(IRQQueue * q, int n_IRQ) +static inline void IRQ_resetbit(struct irq_queue *q, int n_IRQ) { clear_bit(n_IRQ, q->queue); } -static inline int IRQ_testbit(IRQQueue * q, int n_IRQ) +static inline int IRQ_testbit(struct irq_queue *q, int n_IRQ) { return test_bit(n_IRQ, q->queue); } -static void IRQ_check(OpenPICState * opp, IRQQueue * q) +static void IRQ_check(struct openpic *opp, struct irq_queue *q) { int irq = -1; int next = -1; @@ -238,11 +231,10 @@ static void IRQ_check(OpenPICState * opp, IRQQueue * q) for (;;) { irq = find_next_bit(q->queue, opp->max_irq, irq + 1); - if (irq == opp->max_irq) { + if (irq == opp->max_irq) break; - } - DPRINTF("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n", + pr_debug("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n", irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority); if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) { @@ -255,7 +247,7 @@ static void IRQ_check(OpenPICState * opp, IRQQueue * q) q->priority = priority; } -static int IRQ_get_next(OpenPICState * opp, IRQQueue * q) +static int IRQ_get_next(struct openpic *opp, struct irq_queue *q) { /* XXX: optimize */ IRQ_check(opp, q); @@ -263,21 +255,21 @@ static int IRQ_get_next(OpenPICState * opp, IRQQueue * q) return q->next; } -static void IRQ_local_pipe(OpenPICState * opp, int n_CPU, int n_IRQ, +static void IRQ_local_pipe(struct openpic *opp, int n_CPU, int n_IRQ, bool active, bool was_active) { - IRQDest *dst; - IRQSource *src; + struct irq_dest *dst; + struct irq_source *src; int priority; dst = &opp->dst[n_CPU]; src = &opp->src[n_IRQ]; - DPRINTF("%s: IRQ %d active %d was %d\n", + pr_debug("%s: IRQ %d active %d was %d\n", __func__, n_IRQ, active, was_active); if (src->output != OPENPIC_OUTPUT_INT) { - DPRINTF("%s: output %d irq %d active %d was %d count %d\n", + pr_debug("%s: output %d irq %d active %d was %d count %d\n", __func__, src->output, n_IRQ, active, was_active, dst->outputs_active[src->output]); @@ -286,19 +278,17 @@ static void IRQ_local_pipe(OpenPICState * opp, int n_CPU, int n_IRQ, * masking. */ if (active) { - if (!was_active - && dst->outputs_active[src->output]++ == 0) { - DPRINTF - ("%s: Raise OpenPIC output %d cpu %d irq %d\n", - __func__, src->output, n_CPU, n_IRQ); + if (!was_active && + dst->outputs_active[src->output]++ == 0) { + pr_debug("%s: Raise OpenPIC output %d cpu %d irq %d\n", + __func__, src->output, n_CPU, n_IRQ); qemu_irq_raise(dst->irqs[src->output]); } } else { - if (was_active - && --dst->outputs_active[src->output] == 0) { - DPRINTF - ("%s: Lower OpenPIC output %d cpu %d irq %d\n", - __func__, src->output, n_CPU, n_IRQ); + if (was_active && + --dst->outputs_active[src->output] == 0) { + pr_debug("%s: Lower OpenPIC output %d cpu %d irq %d\n", + __func__, src->output, n_CPU, n_IRQ); qemu_irq_lower(dst->irqs[src->output]); } } @@ -311,31 +301,27 @@ static void IRQ_local_pipe(OpenPICState * opp, int n_CPU, int n_IRQ, /* Even if the interrupt doesn't have enough priority, * it is still raised, in case ctpr is lowered later. */ - if (active) { + if (active) IRQ_setbit(&dst->raised, n_IRQ); - } else { + else IRQ_resetbit(&dst->raised, n_IRQ); - } IRQ_check(opp, &dst->raised); if (active && priority <= dst->ctpr) { - DPRINTF - ("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n", - __func__, n_IRQ, priority, dst->ctpr, n_CPU); + pr_debug("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n", + __func__, n_IRQ, priority, dst->ctpr, n_CPU); active = 0; } if (active) { if (IRQ_get_next(opp, &dst->servicing) >= 0 && priority <= dst->servicing.priority) { - DPRINTF - ("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n", - __func__, n_IRQ, dst->servicing.next, n_CPU); + pr_debug("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n", + __func__, n_IRQ, dst->servicing.next, n_CPU); } else { - DPRINTF - ("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n", - __func__, n_CPU, n_IRQ, dst->raised.next); + pr_debug("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n", + __func__, n_CPU, n_IRQ, dst->raised.next); qemu_irq_raise(opp->dst[n_CPU]. irqs[OPENPIC_OUTPUT_INT]); } @@ -343,17 +329,15 @@ static void IRQ_local_pipe(OpenPICState * opp, int n_CPU, int n_IRQ, IRQ_get_next(opp, &dst->servicing); if (dst->raised.priority > dst->ctpr && dst->raised.priority > dst->servicing.priority) { - DPRINTF - ("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n", - __func__, n_IRQ, dst->raised.next, - dst->raised.priority, dst->ctpr, - dst->servicing.priority, n_CPU); + pr_debug("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n", + __func__, n_IRQ, dst->raised.next, + dst->raised.priority, dst->ctpr, + dst->servicing.priority, n_CPU); /* IRQ line stays asserted */ } else { - DPRINTF - ("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n", - __func__, n_IRQ, dst->ctpr, - dst->servicing.priority, n_CPU); + pr_debug("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n", + __func__, n_IRQ, dst->ctpr, + dst->servicing.priority, n_CPU); qemu_irq_lower(opp->dst[n_CPU]. irqs[OPENPIC_OUTPUT_INT]); } @@ -361,9 +345,9 @@ static void IRQ_local_pipe(OpenPICState * opp, int n_CPU, int n_IRQ, } /* update pic state because registers for n_IRQ have changed value */ -static void openpic_update_irq(OpenPICState * opp, int n_IRQ) +static void openpic_update_irq(struct openpic *opp, int n_IRQ) { - IRQSource *src; + struct irq_source *src; bool active, was_active; int i; @@ -372,30 +356,29 @@ static void openpic_update_irq(OpenPICState * opp, int n_IRQ) if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) { /* Interrupt source is disabled */ - DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ); + pr_debug("%s: IRQ %d is disabled\n", __func__, n_IRQ); active = false; } - was_active = ! !(src->ivpr & IVPR_ACTIVITY_MASK); + was_active = !!(src->ivpr & IVPR_ACTIVITY_MASK); /* * We don't have a similar check for already-active because * ctpr may have changed and we need to withdraw the interrupt. */ if (!active && !was_active) { - DPRINTF("%s: IRQ %d is already inactive\n", __func__, n_IRQ); + pr_debug("%s: IRQ %d is already inactive\n", __func__, n_IRQ); return; } - if (active) { + if (active) src->ivpr |= IVPR_ACTIVITY_MASK; - } else { + else src->ivpr &= ~IVPR_ACTIVITY_MASK; - } if (src->destmask == 0) { /* No target */ - DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ); + pr_debug("%s: IRQ %d has no target\n", __func__, n_IRQ); return; } @@ -413,9 +396,9 @@ static void openpic_update_irq(OpenPICState * opp, int n_IRQ) } else { /* Distributed delivery mode */ for (i = src->last_cpu + 1; i != src->last_cpu; i++) { - if (i == opp->nb_cpus) { + if (i == opp->nb_cpus) i = 0; - } + if (src->destmask & (1 << i)) { IRQ_local_pipe(opp, i, n_IRQ, active, was_active); @@ -428,16 +411,16 @@ static void openpic_update_irq(OpenPICState * opp, int n_IRQ) static void openpic_set_irq(void *opaque, int n_IRQ, int level) { - OpenPICState *opp = opaque; - IRQSource *src; + struct openpic *opp = opaque; + struct irq_source *src; if (n_IRQ >= MAX_IRQ) { - fprintf(stderr, "%s: IRQ %d out of range\n", __func__, n_IRQ); + pr_err("%s: IRQ %d out of range\n", __func__, n_IRQ); abort(); } src = &opp->src[n_IRQ]; - DPRINTF("openpic: set irq %d = %d ivpr=0x%08x\n", + pr_debug("openpic: set irq %d = %d ivpr=0x%08x\n", n_IRQ, level, src->ivpr); if (src->level) { /* level-sensitive irq */ @@ -463,9 +446,9 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int level) } } -static void openpic_reset(DeviceState * d) +static void openpic_reset(DeviceState *d) { - OpenPICState *opp = FROM_SYSBUS(typeof(*opp), SYS_BUS_DEVICE(d)); + struct openpic *opp = FROM_SYSBUS(typeof(*opp), SYS_BUS_DEVICE(d)); int i; opp->gcr = GCR_RESET; @@ -485,7 +468,7 @@ static void openpic_reset(DeviceState * d) switch (opp->src[i].type) { case IRQ_TYPE_NORMAL: opp->src[i].level = - ! !(opp->ivpr_reset & IVPR_SENSE_MASK); + !!(opp->ivpr_reset & IVPR_SENSE_MASK); break; case IRQ_TYPE_FSLINT: @@ -499,9 +482,9 @@ static void openpic_reset(DeviceState * d) /* Initialise IRQ destinations */ for (i = 0; i < MAX_CPU; i++) { opp->dst[i].ctpr = 15; - memset(&opp->dst[i].raised, 0, sizeof(IRQQueue)); + memset(&opp->dst[i].raised, 0, sizeof(struct irq_queue)); opp->dst[i].raised.next = -1; - memset(&opp->dst[i].servicing, 0, sizeof(IRQQueue)); + memset(&opp->dst[i].servicing, 0, sizeof(struct irq_queue)); opp->dst[i].servicing.next = -1; } /* Initialise timers */ @@ -513,28 +496,28 @@ static void openpic_reset(DeviceState * d) opp->gcr = 0; } -static inline uint32_t read_IRQreg_idr(OpenPICState * opp, int n_IRQ) +static inline uint32_t read_IRQreg_idr(struct openpic *opp, int n_IRQ) { return opp->src[n_IRQ].idr; } -static inline uint32_t read_IRQreg_ilr(OpenPICState * opp, int n_IRQ) +static inline uint32_t read_IRQreg_ilr(struct openpic *opp, int n_IRQ) { - if (opp->flags & OPENPIC_FLAG_ILR) { + if (opp->flags & OPENPIC_FLAG_ILR) return output_to_inttgt(opp->src[n_IRQ].output); - } return 0xffffffff; } -static inline uint32_t read_IRQreg_ivpr(OpenPICState * opp, int n_IRQ) +static inline uint32_t read_IRQreg_ivpr(struct openpic *opp, int n_IRQ) { return opp->src[n_IRQ].ivpr; } -static inline void write_IRQreg_idr(OpenPICState * opp, int n_IRQ, uint32_t val) +static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ, + uint32_t val) { - IRQSource *src = &opp->src[n_IRQ]; + struct irq_source *src = &opp->src[n_IRQ]; uint32_t normal_mask = (1UL << opp->nb_cpus) - 1; uint32_t crit_mask = 0; uint32_t mask = normal_mask; @@ -547,14 +530,13 @@ static inline void write_IRQreg_idr(OpenPICState * opp, int n_IRQ, uint32_t val) } src->idr = val & mask; - DPRINTF("Set IDR %d to 0x%08x\n", n_IRQ, src->idr); + pr_debug("Set IDR %d to 0x%08x\n", n_IRQ, src->idr); if (opp->flags & OPENPIC_FLAG_IDR_CRIT) { if (src->idr & crit_mask) { if (src->idr & normal_mask) { - DPRINTF - ("%s: IRQ configured for multiple output types, using " - "critical\n", __func__); + pr_debug("%s: IRQ configured for multiple output types, using critical\n", + __func__); } src->output = OPENPIC_OUTPUT_CINT; @@ -564,9 +546,8 @@ static inline void write_IRQreg_idr(OpenPICState * opp, int n_IRQ, uint32_t val) for (i = 0; i < opp->nb_cpus; i++) { int n_ci = IDR_CI0_SHIFT - i; - if (src->idr & (1UL << n_ci)) { + if (src->idr & (1UL << n_ci)) src->destmask |= 1UL << i; - } } } else { src->output = OPENPIC_OUTPUT_INT; @@ -578,20 +559,21 @@ static inline void write_IRQreg_idr(OpenPICState * opp, int n_IRQ, uint32_t val) } } -static inline void write_IRQreg_ilr(OpenPICState * opp, int n_IRQ, uint32_t val) +static inline void write_IRQreg_ilr(struct openpic *opp, int n_IRQ, + uint32_t val) { if (opp->flags & OPENPIC_FLAG_ILR) { - IRQSource *src = &opp->src[n_IRQ]; + struct irq_source *src = &opp->src[n_IRQ]; src->output = inttgt_to_output(val & ILR_INTTGT_MASK); - DPRINTF("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr, + pr_debug("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr, src->output); /* TODO: on MPIC v4.0 only, set nomask for non-INT */ } } -static inline void write_IRQreg_ivpr(OpenPICState * opp, int n_IRQ, +static inline void write_IRQreg_ivpr(struct openpic *opp, int n_IRQ, uint32_t val) { uint32_t mask; @@ -613,7 +595,7 @@ static inline void write_IRQreg_ivpr(OpenPICState * opp, int n_IRQ, switch (opp->src[n_IRQ].type) { case IRQ_TYPE_NORMAL: opp->src[n_IRQ].level = - ! !(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK); + !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK); break; case IRQ_TYPE_FSLINT: @@ -626,11 +608,11 @@ static inline void write_IRQreg_ivpr(OpenPICState * opp, int n_IRQ, } openpic_update_irq(opp, n_IRQ); - DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val, + pr_debug("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val, opp->src[n_IRQ].ivpr); } -static void openpic_gcr_write(OpenPICState * opp, uint64_t val) +static void openpic_gcr_write(struct openpic *opp, uint64_t val) { bool mpic_proxy = false; @@ -643,27 +625,26 @@ static void openpic_gcr_write(OpenPICState * opp, uint64_t val) opp->gcr |= val & opp->mpic_mode_mask; /* Set external proxy mode */ - if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) { + if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) mpic_proxy = true; - } ppce500_set_mpic_proxy(mpic_proxy); } -static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, +static void openpic_gbl_write(void *opaque, gpa_t addr, uint64_t val, unsigned len) { - OpenPICState *opp = opaque; - IRQDest *dst; + struct openpic *opp = opaque; + struct irq_dest *dst; int idx; - DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", + pr_debug("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", __func__, addr, val); - if (addr & 0xF) { + if (addr & 0xF) return; - } + switch (addr) { - case 0x00: /* Block Revision Register1 (BRR1) is Readonly */ + case 0x00: /* Block Revision Register1 (BRR1) is Readonly */ break; case 0x40: case 0x50: @@ -685,16 +666,14 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, case 0x1090: /* PIR */ for (idx = 0; idx < opp->nb_cpus; idx++) { if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) { - DPRINTF - ("Raise OpenPIC RESET output for CPU %d\n", - idx); + pr_debug("Raise OpenPIC RESET output for CPU %d\n", + idx); dst = &opp->dst[idx]; qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]); - } else if (!(val & (1 << idx)) - && (opp->pir & (1 << idx))) { - DPRINTF - ("Lower OpenPIC RESET output for CPU %d\n", - idx); + } else if (!(val & (1 << idx)) && + (opp->pir & (1 << idx))) { + pr_debug("Lower OpenPIC RESET output for CPU %d\n", + idx); dst = &opp->dst[idx]; qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]); } @@ -704,13 +683,12 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, case 0x10A0: /* IPI_IVPR */ case 0x10B0: case 0x10C0: - case 0x10D0: - { - int idx; - idx = (addr - 0x10A0) >> 4; - write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val); - } + case 0x10D0: { + int idx; + idx = (addr - 0x10A0) >> 4; + write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val); break; + } case 0x10E0: /* SPVE */ opp->spve = val & opp->vector_mask; break; @@ -719,16 +697,16 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, } } -static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len) +static uint64_t openpic_gbl_read(void *opaque, gpa_t addr, unsigned len) { - OpenPICState *opp = opaque; + struct openpic *opp = opaque; uint32_t retval; - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); + pr_debug("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); retval = 0xFFFFFFFF; - if (addr & 0xF) { + if (addr & 0xF) return retval; - } + switch (addr) { case 0x1000: /* FRR */ retval = opp->frr; @@ -772,24 +750,23 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len) default: break; } - DPRINTF("%s: => 0x%08x\n", __func__, retval); + pr_debug("%s: => 0x%08x\n", __func__, retval); return retval; } -static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val, +static void openpic_tmr_write(void *opaque, gpa_t addr, uint64_t val, unsigned len) { - OpenPICState *opp = opaque; + struct openpic *opp = opaque; int idx; addr += 0x10f0; - DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", + pr_debug("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", __func__, addr, val); - if (addr & 0xF) { + if (addr & 0xF) return; - } if (addr == 0x10f0) { /* TFRR */ @@ -806,9 +783,9 @@ static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val, case 0x10: /* TBCR */ if ((opp->timers[idx].tccr & TCCR_TOG) != 0 && (val & TBCR_CI) == 0 && - (opp->timers[idx].tbcr & TBCR_CI) != 0) { + (opp->timers[idx].tbcr & TBCR_CI) != 0) opp->timers[idx].tccr &= ~TCCR_TOG; - } + opp->timers[idx].tbcr = val; break; case 0x20: /* TVPR */ @@ -820,16 +797,16 @@ static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val, } } -static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len) +static uint64_t openpic_tmr_read(void *opaque, gpa_t addr, unsigned len) { - OpenPICState *opp = opaque; + struct openpic *opp = opaque; uint32_t retval = -1; int idx; - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); - if (addr & 0xF) { + pr_debug("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); + if (addr & 0xF) goto out; - } + idx = (addr >> 6) & 0x3; if (addr == 0x0) { /* TFRR */ @@ -852,18 +829,18 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len) } out: - DPRINTF("%s: => 0x%08x\n", __func__, retval); + pr_debug("%s: => 0x%08x\n", __func__, retval); return retval; } -static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val, +static void openpic_src_write(void *opaque, gpa_t addr, uint64_t val, unsigned len) { - OpenPICState *opp = opaque; + struct openpic *opp = opaque; int idx; - DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", + pr_debug("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", __func__, addr, val); addr = addr & 0xffff; @@ -884,11 +861,11 @@ static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val, static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len) { - OpenPICState *opp = opaque; + struct openpic *opp = opaque; uint32_t retval; int idx; - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); + pr_debug("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); retval = 0xFFFFFFFF; addr = addr & 0xffff; @@ -906,22 +883,21 @@ static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len) break; } - DPRINTF("%s: => 0x%08x\n", __func__, retval); + pr_debug("%s: => 0x%08x\n", __func__, retval); return retval; } -static void openpic_msi_write(void *opaque, hwaddr addr, uint64_t val, +static void openpic_msi_write(void *opaque, gpa_t addr, uint64_t val, unsigned size) { - OpenPICState *opp = opaque; + struct openpic *opp = opaque; int idx = opp->irq_msi; int srs, ibs; - DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n", + pr_debug("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n", __func__, addr, val); - if (addr & 0xF) { + if (addr & 0xF) return; - } switch (addr) { case MSIIR_OFFSET: @@ -937,16 +913,15 @@ static void openpic_msi_write(void *opaque, hwaddr addr, uint64_t val, } } -static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size) +static uint64_t openpic_msi_read(void *opaque, gpa_t addr, unsigned size) { - OpenPICState *opp = opaque; + struct openpic *opp = opaque; uint64_t r = 0; int i, srs; - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); - if (addr & 0xF) { + pr_debug("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); + if (addr & 0xF) return -1; - } srs = addr >> 4; @@ -965,53 +940,51 @@ static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size) openpic_set_irq(opp, opp->irq_msi + srs, 0); break; case 0x120: /* MSISR */ - for (i = 0; i < MAX_MSI; i++) { + for (i = 0; i < MAX_MSI; i++) r |= (opp->msi[i].msir ? 1 : 0) << i; - } break; } return r; } -static uint64_t openpic_summary_read(void *opaque, hwaddr addr, unsigned size) +static uint64_t openpic_summary_read(void *opaque, gpa_t addr, unsigned size) { uint64_t r = 0; - DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); + pr_debug("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); /* TODO: EISR/EIMR */ return r; } -static void openpic_summary_write(void *opaque, hwaddr addr, uint64_t val, +static void openpic_summary_write(void *opaque, gpa_t addr, uint64_t val, unsigned size) { - DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n", + pr_debug("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n", __func__, addr, val); /* TODO: EISR/EIMR */ } -static void openpic_cpu_write_internal(void *opaque, hwaddr addr, +static void openpic_cpu_write_internal(void *opaque, gpa_t addr, uint32_t val, int idx) { - OpenPICState *opp = opaque; - IRQSource *src; - IRQDest *dst; + struct openpic *opp = opaque; + struct irq_source *src; + struct irq_dest *dst; int s_IRQ, n_IRQ; - DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx " <= 0x%08x\n", __func__, idx, + pr_debug("%s: cpu %d addr %#" HWADDR_PRIx " <= 0x%08x\n", __func__, idx, addr, val); - if (idx < 0) { + if (idx < 0) return; - } - if (addr & 0xF) { + if (addr & 0xF) return; - } + dst = &opp->dst[idx]; addr &= 0xFF0; switch (addr) { @@ -1028,17 +1001,16 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr, case 0x80: /* CTPR */ dst->ctpr = val & 0x0000000F; - DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d\n", + pr_debug("%s: set CPU %d ctpr to %d, raised %d servicing %d\n", __func__, idx, dst->ctpr, dst->raised.priority, dst->servicing.priority); if (dst->raised.priority <= dst->ctpr) { - DPRINTF - ("%s: Lower OpenPIC INT output cpu %d due to ctpr\n", - __func__, idx); + pr_debug("%s: Lower OpenPIC INT output cpu %d due to ctpr\n", + __func__, idx); qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); } else if (dst->raised.priority > dst->servicing.priority) { - DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d\n", + pr_debug("%s: Raise OpenPIC INT output cpu %d irq %d\n", __func__, idx, dst->raised.next); qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]); } @@ -1051,11 +1023,11 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr, /* Read-only register */ break; case 0xB0: /* EOI */ - DPRINTF("EOI\n"); + pr_debug("EOI\n"); s_IRQ = IRQ_get_next(opp, &dst->servicing); if (s_IRQ < 0) { - DPRINTF("%s: EOI with no interrupt in service\n", + pr_debug("%s: EOI with no interrupt in service\n", __func__); break; } @@ -1069,7 +1041,7 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr, if (n_IRQ != -1 && (s_IRQ == -1 || IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) { - DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", + pr_debug("Raise OpenPIC INT output cpu %d irq %d\n", idx, n_IRQ); qemu_irq_raise(opp->dst[idx].irqs[OPENPIC_OUTPUT_INT]); } @@ -1079,32 +1051,32 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr, } } -static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val, +static void openpic_cpu_write(void *opaque, gpa_t addr, uint64_t val, unsigned len) { openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12); } -static uint32_t openpic_iack(OpenPICState * opp, IRQDest * dst, int cpu) +static uint32_t openpic_iack(struct openpic *opp, struct irq_dest *dst, + int cpu) { - IRQSource *src; + struct irq_source *src; int retval, irq; - DPRINTF("Lower OpenPIC INT output\n"); + pr_debug("Lower OpenPIC INT output\n"); qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); irq = IRQ_get_next(opp, &dst->raised); - DPRINTF("IACK: irq=%d\n", irq); + pr_debug("IACK: irq=%d\n", irq); - if (irq == -1) { + if (irq == -1) /* No more interrupt pending */ return opp->spve; - } src = &opp->src[irq]; if (!(src->ivpr & IVPR_ACTIVITY_MASK) || !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) { - fprintf(stderr, "%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n", + pr_err("%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n", __func__, irq, dst->ctpr, src->ivpr); openpic_update_irq(opp, irq); retval = opp->spve; @@ -1135,22 +1107,21 @@ static uint32_t openpic_iack(OpenPICState * opp, IRQDest * dst, int cpu) return retval; } -static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, int idx) +static uint32_t openpic_cpu_read_internal(void *opaque, gpa_t addr, int idx) { - OpenPICState *opp = opaque; - IRQDest *dst; + struct openpic *opp = opaque; + struct irq_dest *dst; uint32_t retval; - DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx "\n", __func__, idx, addr); + pr_debug("%s: cpu %d addr %#" HWADDR_PRIx "\n", __func__, idx, addr); retval = 0xFFFFFFFF; - if (idx < 0) { + if (idx < 0) return retval; - } - if (addr & 0xF) { + if (addr & 0xF) return retval; - } + dst = &opp->dst[idx]; addr &= 0xFF0; switch (addr) { @@ -1169,54 +1140,54 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, int idx) default: break; } - DPRINTF("%s: => 0x%08x\n", __func__, retval); + pr_debug("%s: => 0x%08x\n", __func__, retval); return retval; } -static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len) +static uint64_t openpic_cpu_read(void *opaque, gpa_t addr, unsigned len) { return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12); } -static const MemoryRegionOps openpic_glb_ops_be = { +static const struct kvm_io_device_ops openpic_glb_ops_be = { .write = openpic_gbl_write, .read = openpic_gbl_read, }; -static const MemoryRegionOps openpic_tmr_ops_be = { +static const struct kvm_io_device_ops openpic_tmr_ops_be = { .write = openpic_tmr_write, .read = openpic_tmr_read, }; -static const MemoryRegionOps openpic_cpu_ops_be = { +static const struct kvm_io_device_ops openpic_cpu_ops_be = { .write = openpic_cpu_write, .read = openpic_cpu_read, }; -static const MemoryRegionOps openpic_src_ops_be = { +static const struct kvm_io_device_ops openpic_src_ops_be = { .write = openpic_src_write, .read = openpic_src_read, }; -static const MemoryRegionOps openpic_msi_ops_be = { +static const struct kvm_io_device_ops openpic_msi_ops_be = { .read = openpic_msi_read, .write = openpic_msi_write, }; -static const MemoryRegionOps openpic_summary_ops_be = { +static const struct kvm_io_device_ops openpic_summary_ops_be = { .read = openpic_summary_read, .write = openpic_summary_write, }; -typedef struct MemReg { +struct mem_reg { const char *name; - MemoryRegionOps const *ops; - hwaddr start_addr; - ram_addr_t size; -} MemReg; + const struct kvm_io_device_ops *ops; + gpa_t start_addr; + int size; +}; -static void fsl_common_init(OpenPICState * opp) +static void fsl_common_init(struct openpic *opp) { int i; int virq = MAX_SRC; @@ -1239,9 +1210,8 @@ static void fsl_common_init(OpenPICState * opp) opp->irq_msi = 224; msi_supported = true; - for (i = 0; i < opp->fsl->max_ext; i++) { + for (i = 0; i < opp->fsl->max_ext; i++) opp->src[i].level = false; - } /* Internal interrupts, including message and MSI */ for (i = 16; i < MAX_SRC; i++) { @@ -1256,7 +1226,8 @@ static void fsl_common_init(OpenPICState * opp) } } -static void map_list(OpenPICState * opp, const MemReg * list, int *count) +static void map_list(struct openpic *opp, const struct mem_reg *list, + int *count) { while (list->name) { assert(*count < ARRAY_SIZE(opp->sub_io_mem)); @@ -1272,12 +1243,12 @@ static void map_list(OpenPICState * opp, const MemReg * list, int *count) } } -static int openpic_init(SysBusDevice * dev) +static int openpic_init(SysBusDevice *dev) { - OpenPICState *opp = FROM_SYSBUS(typeof(*opp), dev); + struct openpic *opp = FROM_SYSBUS(typeof(*opp), dev); int i, j; int list_count = 0; - static const MemReg list_le[] = { + static const struct mem_reg list_le[] = { {"glb", &openpic_glb_ops_le, OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE}, {"tmr", &openpic_tmr_ops_le, @@ -1288,7 +1259,7 @@ static int openpic_init(SysBusDevice * dev) OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE}, {NULL} }; - static const MemReg list_be[] = { + static const struct mem_reg list_be[] = { {"glb", &openpic_glb_ops_be, OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE}, {"tmr", &openpic_tmr_ops_be, @@ -1299,7 +1270,7 @@ static int openpic_init(SysBusDevice * dev) OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE}, {NULL} }; - static const MemReg list_fsl[] = { + static const struct mem_reg list_fsl[] = { {"msi", &openpic_msi_ops_be, OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE}, {"summary", &openpic_summary_ops_be,