From patchwork Fri Apr 26 13:22:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Greenhalgh X-Patchwork-Id: 239871 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id DEF232C00D6 for ; Fri, 26 Apr 2013 23:22:35 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=iFTlsdNUCNjsxSQzWE5VzjfRuw9BdF09+jbIUqpm2adEu3ZgHE EuTc2yciStnO6RwNDHZjdYwvtE3O53Ujv1UN29QG4UOScOI0TCrKjr+9+wF+IZlp 4miFdwhI5s/FF5at03FghNjo9UEEHK2QzuE9VSnmq80fcLwVrRSPvlDyQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=93TWPd2hcI0FuafDyGisWCoQSz4=; b=nq2rjOse1SverOf5GlYo OJl/PVH8bMfrpJrmcxwk5aUDFYuEyeexDnsIBQnwzaz8r40UljFJFKnEe8v/kEyX 56wV3gEH8kRMu/8ntaS6XYRDso5TpUWEUG3OpU2FcL1wfTFphJ/nx5W6vA8nvVAK OXr3i9NvbLLH278ZGJuQRlQ= Received: (qmail 26294 invoked by alias); 26 Apr 2013 13:22:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 26187 invoked by uid 89); 26 Apr 2013 13:22:28 -0000 X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS, TW_FC autolearn=ham version=3.3.1 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Fri, 26 Apr 2013 13:22:28 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 26 Apr 2013 14:22:25 +0100 Received: from e106375-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 26 Apr 2013 14:22:23 +0100 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: marcus.shawcroft@arm.com Subject: [AArch64] Add vector int to float conversions. Date: Fri, 26 Apr 2013 14:22:19 +0100 Message-Id: <1366982539-14080-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: 113042614222510401 X-Virus-Found: No Hi, This patch wires up builtins for int to float conversions in Tree, and uint to float conversions in RTL. Regression tested for aarch64-none-elf with no regressions. Thanks, James --- gcc/ 2013-04-26 James Greenhalgh * config/aarch64/aarch64-builtins.c (aarch64_fold_builtin): Fold float conversions. * config/aarch64/aarch64-simd-builtins.def (floatv2si, floatv4si, floatv2di): New. (floatunsv2si, floatunsv4si, floatunsv2di): Likewise. * config/aarch64/aarch64-simd.md (2): New, expands to float and floatuns. * config/aarch64/iterators.md (FLOATUORS): New. (optab): Add float, floatuns. (su_optab): Likewise. diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index f540568..d2e5136 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -1296,6 +1296,11 @@ aarch64_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args, BUILTIN_VDQF (UNOP, abs, 2) return fold_build1 (ABS_EXPR, type, args[0]); break; + VAR1 (UNOP, floatv2si, 2, v2sf) + VAR1 (UNOP, floatv4si, 2, v4sf) + VAR1 (UNOP, floatv2di, 2, v2df) + return fold_build1 (FLOAT_EXPR, type, args[0]); + break; default: break; } diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 4654bd5..029e091 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -310,6 +310,15 @@ VAR1 (UNOP, lfrintnusf, 2, si) VAR1 (UNOP, lfrintnudf, 2, di) + /* Implemented by 2. */ + VAR1 (UNOP, floatv2si, 2, v2sf) + VAR1 (UNOP, floatv4si, 2, v4sf) + VAR1 (UNOP, floatv2di, 2, v2df) + + VAR1 (UNOP, floatunsv2si, 2, v2sf) + VAR1 (UNOP, floatunsv4si, 2, v4sf) + VAR1 (UNOP, floatunsv2di, 2, v2df) + /* Implemented by aarch64_. */ BUILTIN_VALL (BINOP, zip1, 0) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 4c678ba..067c849 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1257,6 +1257,16 @@ (set_attr "simd_mode" "")] ) +(define_insn "2" + [(set (match_operand:VDQF 0 "register_operand" "=w") + (FLOATUORS:VDQF + (match_operand: 1 "register_operand" "w")))] + "TARGET_SIMD" + "cvtf\\t%0., %1." + [(set_attr "simd_type" "simd_icvtf") + (set_attr "simd_mode" "")] +) + (define_insn "aarch64_vmls" [(set (match_operand:VDQF 0 "register_operand" "=w") (minus:VDQF (match_operand:VDQF 1 "register_operand" "0") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 5c769f8..8668d3f 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -530,6 +530,9 @@ ;; Iterator for integer conversions (define_code_iterator FIXUORS [fix unsigned_fix]) +;; Iterator for float conversions +(define_code_iterator FLOATUORS [float unsigned_float]) + ;; Code iterator for variants of vector max and min. (define_code_iterator MAXMIN [smax smin umax umin]) @@ -557,6 +560,8 @@ (zero_extend "zero_extend") (sign_extract "extv") (zero_extract "extzv") + (float "float") + (unsigned_float "floatuns") (and "and") (ior "ior") (xor "xor") @@ -579,6 +584,7 @@ (define_code_attr su_optab [(sign_extend "") (zero_extend "u") (div "") (udiv "u") (fix "") (unsigned_fix "u") + (float "s") (unsigned_float "u") (ss_plus "s") (us_plus "u") (ss_minus "s") (us_minus "u")])