From patchwork Fri Apr 26 13:12:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Greenhalgh X-Patchwork-Id: 239864 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id B7E4E2C0109 for ; Fri, 26 Apr 2013 23:12:40 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=IHZufNN+mKYnm7EJgXalnoUNUKjEDH/PBuubor6oD25tGQI8ax rF5QhwCeHV6XxkwPhxoMFyyrEt50x3eNgwamlyCOqRXCgaJRRwfhK2I3+lqerUc8 K26S0ZNpmciieVcrNPWjmucmshNwEloYig0MhCcf/gPxX6JMzKeIvOsmU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=kc6bUZd21c/7g2CiTLJwYDX7DsE=; b=Ptqb33RNw3KkfzxBkJtU 751Z3LDpM896TuO1KQODuvHeoU2pbKhuFuWBrHKsBEFCg8VYEDKtpa7U/UaPj9LT zU1dQTofpGkxoQOqhpkYQWIQor7ySYDJzTUmCvAuF6WHehNu1qUgLDyyEgagXHdk 0TvQJXqG5tSpXjZYy8CLJCQ= Received: (qmail 14151 invoked by alias); 26 Apr 2013 13:12:33 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 14140 invoked by uid 89); 26 Apr 2013 13:12:33 -0000 X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS, TW_FC, TW_VC autolearn=ham version=3.3.1 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Fri, 26 Apr 2013 13:12:31 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 26 Apr 2013 14:12:29 +0100 Received: from e106375-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 26 Apr 2013 14:12:26 +0100 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: marcus.shawcroft@arm.com Subject: [AArch64] Map fcvt intrinsics to builtin name directly. Date: Fri, 26 Apr 2013 14:12:22 +0100 Message-Id: <1366981942-21584-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: 113042614122910901 X-Virus-Found: No Hi, This patch uses the new builtin-mapping infrastructure to map the fcvt family of builtins directly to their GCC standard pattern name. Regression tested on aarch64-none-elf with no regressions. Thanks, James --- gcc/ 2013-04-26 James Greenhalgh * config/aarch64/aarch64-builtins.c (aarch64_builtin_vectorized_function): Use new names for fcvt builtins. * config/aarch64/aarch64-simd-builtins.def (fcvtzs): Split as... (lbtruncv2sf, lbtruncv4sf, lbtruncv2df): ...This. (fcvtzu): Split as... (lbtruncuv2sf, lbtruncuv4sf, lbtruncuv2df): ...This. (fcvtas): Split as... (lroundv2sf, lroundv4sf, lroundv2df, lroundsf, lrounddf): ...This. (fcvtau): Split as... (lrounduv2sf, lrounduv4sf, lrounduv2df, lroundusf, lroundudf): ...This. (fcvtps): Split as... (lceilv2sf, lceilv4sf, lceilv2df): ...This. (fcvtpu): Split as... (lceiluv2sf, lceiluv4sf, lceiluv2df, lceilusf, lceiludf): ...This. (fcvtms): Split as... (lfloorv2sf, lfloorv4sf, lfloorv2df): ...This. (fcvtmu): Split as... (lflooruv2sf, lflooruv4sf, lflooruv2df, lfloorusf, lfloorudf): ...This. (lfrintnv2sf, lfrintnv4sf, lfrintnv2df, lfrintnsf, lfrintndf): New. (lfrintnuv2sf, lfrintnuv4sf, lfrintnuv2df): Likewise. (lfrintnusf, lfrintnudf): Likewise. * config/aarch64/aarch64-simd.md (l2): Convert to define_insn. (aarch64_fcvt): Remove. * config/aarch64/iterators.md (FCVT): Include UNSPEC_FRINTN. (fcvt_pattern): Likewise. diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 08bfe01..f540568 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -1245,9 +1245,33 @@ aarch64_builtin_vectorized_function (tree fndecl, tree type_out, tree type_in) (out_mode == N##Imode && out_n == C \ && in_mode == N##Fmode && in_n == C) case BUILT_IN_LFLOOR: - return AARCH64_FIND_FRINT_VARIANT (fcvtms); + { + tree new_tree = NULL_TREE; + if (AARCH64_CHECK_BUILTIN_MODE (2, D)) + new_tree = + aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lfloorv2dfv2di]; + else if (AARCH64_CHECK_BUILTIN_MODE (4, S)) + new_tree = + aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lfloorv4sfv4si]; + else if (AARCH64_CHECK_BUILTIN_MODE (2, S)) + new_tree = + aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lfloorv2sfv2si]; + return new_tree; + } case BUILT_IN_LCEIL: - return AARCH64_FIND_FRINT_VARIANT (fcvtps); + { + tree new_tree = NULL_TREE; + if (AARCH64_CHECK_BUILTIN_MODE (2, D)) + new_tree = + aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lceilv2dfv2di]; + else if (AARCH64_CHECK_BUILTIN_MODE (4, S)) + new_tree = + aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lceilv4sfv4si]; + else if (AARCH64_CHECK_BUILTIN_MODE (2, S)) + new_tree = + aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lceilv2sfv2si]; + return new_tree; + } default: return NULL_TREE; } diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 9b06a68..4654bd5 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -256,15 +256,59 @@ BUILTIN_VDQF (UNOP, round, 2) BUILTIN_VDQF (UNOP, frintn, 2) - /* Implemented by aarch64_fcvt. */ - BUILTIN_VDQF (UNOP, fcvtzs, 0) - BUILTIN_VDQF (UNOP, fcvtzu, 0) - BUILTIN_VDQF (UNOP, fcvtas, 0) - BUILTIN_VDQF (UNOP, fcvtau, 0) - BUILTIN_VDQF (UNOP, fcvtps, 0) - BUILTIN_VDQF (UNOP, fcvtpu, 0) - BUILTIN_VDQF (UNOP, fcvtms, 0) - BUILTIN_VDQF (UNOP, fcvtmu, 0) + /* Implemented by l2. */ + VAR1 (UNOP, lbtruncv2sf, 2, v2si) + VAR1 (UNOP, lbtruncv4sf, 2, v4si) + VAR1 (UNOP, lbtruncv2df, 2, v2di) + + VAR1 (UNOP, lbtruncuv2sf, 2, v2si) + VAR1 (UNOP, lbtruncuv4sf, 2, v4si) + VAR1 (UNOP, lbtruncuv2df, 2, v2di) + + VAR1 (UNOP, lroundv2sf, 2, v2si) + VAR1 (UNOP, lroundv4sf, 2, v4si) + VAR1 (UNOP, lroundv2df, 2, v2di) + /* Implemented by l2. */ + VAR1 (UNOP, lroundsf, 2, si) + VAR1 (UNOP, lrounddf, 2, di) + + VAR1 (UNOP, lrounduv2sf, 2, v2si) + VAR1 (UNOP, lrounduv4sf, 2, v4si) + VAR1 (UNOP, lrounduv2df, 2, v2di) + VAR1 (UNOP, lroundusf, 2, si) + VAR1 (UNOP, lroundudf, 2, di) + + VAR1 (UNOP, lceilv2sf, 2, v2si) + VAR1 (UNOP, lceilv4sf, 2, v4si) + VAR1 (UNOP, lceilv2df, 2, v2di) + + VAR1 (UNOP, lceiluv2sf, 2, v2si) + VAR1 (UNOP, lceiluv4sf, 2, v4si) + VAR1 (UNOP, lceiluv2df, 2, v2di) + VAR1 (UNOP, lceilusf, 2, si) + VAR1 (UNOP, lceiludf, 2, di) + + VAR1 (UNOP, lfloorv2sf, 2, v2si) + VAR1 (UNOP, lfloorv4sf, 2, v4si) + VAR1 (UNOP, lfloorv2df, 2, v2di) + + VAR1 (UNOP, lflooruv2sf, 2, v2si) + VAR1 (UNOP, lflooruv4sf, 2, v4si) + VAR1 (UNOP, lflooruv2df, 2, v2di) + VAR1 (UNOP, lfloorusf, 2, si) + VAR1 (UNOP, lfloorudf, 2, di) + + VAR1 (UNOP, lfrintnv2sf, 2, v2si) + VAR1 (UNOP, lfrintnv4sf, 2, v4si) + VAR1 (UNOP, lfrintnv2df, 2, v2di) + VAR1 (UNOP, lfrintnsf, 2, si) + VAR1 (UNOP, lfrintndf, 2, di) + + VAR1 (UNOP, lfrintnuv2sf, 2, v2si) + VAR1 (UNOP, lfrintnuv4sf, 2, v4si) + VAR1 (UNOP, lfrintnuv2df, 2, v2di) + VAR1 (UNOP, lfrintnusf, 2, si) + VAR1 (UNOP, lfrintnudf, 2, di) /* Implemented by aarch64_. */ diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index b716fbe..4c678ba 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1244,7 +1244,9 @@ (set_attr "simd_mode" "")] ) -(define_insn "aarch64_fcvt" +;; Vector versions of the fcvt standard patterns. +;; Expands to lbtrunc, lround, lceil, lfloor +(define_insn "l2" [(set (match_operand: 0 "register_operand" "=w") (FIXUORS: (unspec: [(match_operand:VDQF 1 "register_operand" "w")] @@ -1255,16 +1257,6 @@ (set_attr "simd_mode" "")] ) -;; Vector versions of the fcvt standard patterns. -;; Expands to lbtrunc, lround, lceil, lfloor -(define_expand "l2" - [(set (match_operand: 0 "register_operand") - (FIXUORS: (unspec: - [(match_operand:VDQF 1 "register_operand")] - FCVT)))] - "TARGET_SIMD" - {}) - (define_insn "aarch64_vmls" [(set (match_operand:VDQF 0 "register_operand" "=w") (minus:VDQF (match_operand:VDQF 1 "register_operand" "0") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index a2ad866..5c769f8 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -696,7 +696,7 @@ UNSPEC_FRINTA]) (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM - UNSPEC_FRINTA]) + UNSPEC_FRINTA UNSPEC_FRINTN]) (define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX]) @@ -798,7 +798,8 @@ (UNSPEC_FRINTN "n")]) (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round") - (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")]) + (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor") + (UNSPEC_FRINTN "frintn")]) (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip") (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")