@@ -1245,9 +1245,33 @@ aarch64_builtin_vectorized_function (tree fndecl, tree type_out, tree type_in)
(out_mode == N##Imode && out_n == C \
&& in_mode == N##Fmode && in_n == C)
case BUILT_IN_LFLOOR:
- return AARCH64_FIND_FRINT_VARIANT (fcvtms);
+ {
+ tree new_tree = NULL_TREE;
+ if (AARCH64_CHECK_BUILTIN_MODE (2, D))
+ new_tree =
+ aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lfloorv2dfv2di];
+ else if (AARCH64_CHECK_BUILTIN_MODE (4, S))
+ new_tree =
+ aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lfloorv4sfv4si];
+ else if (AARCH64_CHECK_BUILTIN_MODE (2, S))
+ new_tree =
+ aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lfloorv2sfv2si];
+ return new_tree;
+ }
case BUILT_IN_LCEIL:
- return AARCH64_FIND_FRINT_VARIANT (fcvtps);
+ {
+ tree new_tree = NULL_TREE;
+ if (AARCH64_CHECK_BUILTIN_MODE (2, D))
+ new_tree =
+ aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lceilv2dfv2di];
+ else if (AARCH64_CHECK_BUILTIN_MODE (4, S))
+ new_tree =
+ aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lceilv4sfv4si];
+ else if (AARCH64_CHECK_BUILTIN_MODE (2, S))
+ new_tree =
+ aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lceilv2sfv2si];
+ return new_tree;
+ }
default:
return NULL_TREE;
}
@@ -256,15 +256,59 @@
BUILTIN_VDQF (UNOP, round, 2)
BUILTIN_VDQF (UNOP, frintn, 2)
- /* Implemented by aarch64_fcvt<frint_suffix><su><mode>. */
- BUILTIN_VDQF (UNOP, fcvtzs, 0)
- BUILTIN_VDQF (UNOP, fcvtzu, 0)
- BUILTIN_VDQF (UNOP, fcvtas, 0)
- BUILTIN_VDQF (UNOP, fcvtau, 0)
- BUILTIN_VDQF (UNOP, fcvtps, 0)
- BUILTIN_VDQF (UNOP, fcvtpu, 0)
- BUILTIN_VDQF (UNOP, fcvtms, 0)
- BUILTIN_VDQF (UNOP, fcvtmu, 0)
+ /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2. */
+ VAR1 (UNOP, lbtruncv2sf, 2, v2si)
+ VAR1 (UNOP, lbtruncv4sf, 2, v4si)
+ VAR1 (UNOP, lbtruncv2df, 2, v2di)
+
+ VAR1 (UNOP, lbtruncuv2sf, 2, v2si)
+ VAR1 (UNOP, lbtruncuv4sf, 2, v4si)
+ VAR1 (UNOP, lbtruncuv2df, 2, v2di)
+
+ VAR1 (UNOP, lroundv2sf, 2, v2si)
+ VAR1 (UNOP, lroundv4sf, 2, v4si)
+ VAR1 (UNOP, lroundv2df, 2, v2di)
+ /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2. */
+ VAR1 (UNOP, lroundsf, 2, si)
+ VAR1 (UNOP, lrounddf, 2, di)
+
+ VAR1 (UNOP, lrounduv2sf, 2, v2si)
+ VAR1 (UNOP, lrounduv4sf, 2, v4si)
+ VAR1 (UNOP, lrounduv2df, 2, v2di)
+ VAR1 (UNOP, lroundusf, 2, si)
+ VAR1 (UNOP, lroundudf, 2, di)
+
+ VAR1 (UNOP, lceilv2sf, 2, v2si)
+ VAR1 (UNOP, lceilv4sf, 2, v4si)
+ VAR1 (UNOP, lceilv2df, 2, v2di)
+
+ VAR1 (UNOP, lceiluv2sf, 2, v2si)
+ VAR1 (UNOP, lceiluv4sf, 2, v4si)
+ VAR1 (UNOP, lceiluv2df, 2, v2di)
+ VAR1 (UNOP, lceilusf, 2, si)
+ VAR1 (UNOP, lceiludf, 2, di)
+
+ VAR1 (UNOP, lfloorv2sf, 2, v2si)
+ VAR1 (UNOP, lfloorv4sf, 2, v4si)
+ VAR1 (UNOP, lfloorv2df, 2, v2di)
+
+ VAR1 (UNOP, lflooruv2sf, 2, v2si)
+ VAR1 (UNOP, lflooruv4sf, 2, v4si)
+ VAR1 (UNOP, lflooruv2df, 2, v2di)
+ VAR1 (UNOP, lfloorusf, 2, si)
+ VAR1 (UNOP, lfloorudf, 2, di)
+
+ VAR1 (UNOP, lfrintnv2sf, 2, v2si)
+ VAR1 (UNOP, lfrintnv4sf, 2, v4si)
+ VAR1 (UNOP, lfrintnv2df, 2, v2di)
+ VAR1 (UNOP, lfrintnsf, 2, si)
+ VAR1 (UNOP, lfrintndf, 2, di)
+
+ VAR1 (UNOP, lfrintnuv2sf, 2, v2si)
+ VAR1 (UNOP, lfrintnuv4sf, 2, v4si)
+ VAR1 (UNOP, lfrintnuv2df, 2, v2di)
+ VAR1 (UNOP, lfrintnusf, 2, si)
+ VAR1 (UNOP, lfrintnudf, 2, di)
/* Implemented by
aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */
@@ -1244,7 +1244,9 @@
(set_attr "simd_mode" "<MODE>")]
)
-(define_insn "aarch64_fcvt<frint_suffix><su><mode>"
+;; Vector versions of the fcvt standard patterns.
+;; Expands to lbtrunc, lround, lceil, lfloor
+(define_insn "l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2"
[(set (match_operand:<FCVT_TARGET> 0 "register_operand" "=w")
(FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET>
[(match_operand:VDQF 1 "register_operand" "w")]
@@ -1255,16 +1257,6 @@
(set_attr "simd_mode" "<MODE>")]
)
-;; Vector versions of the fcvt standard patterns.
-;; Expands to lbtrunc, lround, lceil, lfloor
-(define_expand "l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2"
- [(set (match_operand:<FCVT_TARGET> 0 "register_operand")
- (FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET>
- [(match_operand:VDQF 1 "register_operand")]
- FCVT)))]
- "TARGET_SIMD"
- {})
-
(define_insn "aarch64_vmls<mode>"
[(set (match_operand:VDQF 0 "register_operand" "=w")
(minus:VDQF (match_operand:VDQF 1 "register_operand" "0")
@@ -696,7 +696,7 @@
UNSPEC_FRINTA])
(define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
- UNSPEC_FRINTA])
+ UNSPEC_FRINTA UNSPEC_FRINTN])
(define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
@@ -798,7 +798,8 @@
(UNSPEC_FRINTN "n")])
(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
- (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")])
+ (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
+ (UNSPEC_FRINTN "frintn")])
(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
(UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")