Patchwork [AArch64] Fix order of modes to lroundmn2 standard names.

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Submitter James Greenhalgh
Date April 26, 2013, 1:09 p.m.
Message ID <1366981773-25621-1-git-send-email-james.greenhalgh@arm.com>
Download mbox | patch
Permalink /patch/239862/
State New
Headers show

Comments

James Greenhalgh - April 26, 2013, 1:09 p.m.
Hi,

The vector versions of lroundmn2, lfloormn2, lceilmn2 convert from
mode m to mode n. The current implementation has this backwards.
For correctness, this patch swaps the n and m parameters.

There is no need to backport this patch as a bug fix, as nothing uses
this name for expansion in 4.8.

Regression tested on aarch64-none-elf with no regressions.

Thanks,
James Greenhalgh

---
gcc/

3013-04-26  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64-simd.md
	(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Rename to...
	(l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2): ... This.
Marcus Shawcroft - April 26, 2013, 1:21 p.m.
On 26/04/13 14:09, James Greenhalgh wrote:
>
> Hi,
>
> The vector versions of lroundmn2, lfloormn2, lceilmn2 convert from
> mode m to mode n. The current implementation has this backwards.
> For correctness, this patch swaps the n and m parameters.
>
> There is no need to backport this patch as a bug fix, as nothing uses
> this name for expansion in 4.8.
>
> Regression tested on aarch64-none-elf with no regressions.
>
> Thanks,
> James Greenhalgh
>
> ---
> gcc/
>
> 3013-04-26  James Greenhalgh  <james.greenhalgh@arm.com>
>
> 	* config/aarch64/aarch64-simd.md
> 	(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Rename to...
> 	(l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2): ... This.
>

OK
/Marcus

Patch

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 5f14cc6..b716fbe 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1257,7 +1257,7 @@ 
 
 ;; Vector versions of the fcvt standard patterns.
 ;; Expands to lbtrunc, lround, lceil, lfloor
-(define_expand "l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2"
+(define_expand "l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2"
   [(set (match_operand:<FCVT_TARGET> 0 "register_operand")
 	(FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET>
 			       [(match_operand:VDQF 1 "register_operand")]