Patchwork [AArch64] Testcases for ANDS instruction

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Submitter Ian Bolton
Date April 26, 2013, 12:54 p.m.
Message ID <000001ce427d$3e8f7fa0$bbae7ee0$@bolton@arm.com>
Download mbox | patch
Permalink /patch/239860/
State New
Headers show

Comments

Ian Bolton - April 26, 2013, 12:54 p.m.
I made some testcases to go with my implementation of ANDS in the backend,
but Naveen Hurugalawadi got the ANDS patterns in before me!
 
I'm now just left with the testcases, but they are still worth adding, so
here they are.

Tests are working correctly as of current trunk.

OK to commit?

Cheers,
Ian


2013-04-26  Ian Bolton  <ian.bolton@arm.com>

       * gcc.target/aarch64/ands.c: New test.
       * gcc.target/aarch64/ands2.c: Likewise
Richard Earnshaw - April 26, 2013, 1:25 p.m.
On 26/04/13 13:54, Ian Bolton wrote:
> I made some testcases to go with my implementation of ANDS in the backend,
> but Naveen Hurugalawadi got the ANDS patterns in before me!
>
> I'm now just left with the testcases, but they are still worth adding, so
> here they are.
>
> Tests are working correctly as of current trunk.
>
> OK to commit?
>
> Cheers,
> Ian
>
>
> 2013-04-26  Ian Bolton  <ian.bolton@arm.com>
>
>         * gcc.target/aarch64/ands.c: New test.
>         * gcc.target/aarch64/ands2.c: Likewise
>
>
> aarch64-ands-tests-svn-patch-v2.txt
>
>
> Index: gcc/testsuite/gcc.target/aarch64/ands2.c
> ===================================================================
> --- gcc/testsuite/gcc.target/aarch64/ands2.c	(revision 0)
> +++ gcc/testsuite/gcc.target/aarch64/ands2.c	(revision 0)
> @@ -0,0 +1,157 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 --save-temps -fno-inline" } */
> +
> +extern void abort (void);
> +
> +int
> +ands_si_test1 (int a, int b, int c)
> +{
> +  int d = a & b;
> +
> +  /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */

This rule
> +  /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */

Will match anything that this rule

> +  /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */

matches (though not vice versa).

Similarly for the x register variants.



R.
Marcus Shawcroft - May 7, 2013, 1:46 p.m.
On 1 May 2013 10:50, Ian Bolton <ian.bolton@arm.com> wrote:

> Thanks for the review. I've fixed this up in the attached patch, by
> counting the number of matches for the first rule and expecting it to
> match additional times to cover the overlap with the lsl based rule.
>
> I've also renamed the testcases in line with the suggested GCC testcase
> naming convention.
>
> OK for commit?
>
> Cheers,
> Ian
>
>
> 2013-05-01  Ian Bolton  <ian.bolton@arm.com>
>
>         * gcc.target/aarch64/ands_1.c: New test.
>         * gcc.target/aarch64/ands_2.c: Likewise

OK
/Marcus

Patch

Index: gcc/testsuite/gcc.target/aarch64/ands2.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/ands2.c	(revision 0)
+++ gcc/testsuite/gcc.target/aarch64/ands2.c	(revision 0)
@@ -0,0 +1,157 @@ 
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+ands_si_test1 (int a, int b, int c)
+{
+  int d = a & b;
+
+  /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+ands_si_test2 (int a, int b, int c)
+{
+  int d = a & 0x99999999;
+
+  /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
+  /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+ands_si_test3 (int a, int b, int c)
+{
+  int d = a & (b << 3);
+
+  /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+ands_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & b;
+
+  /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+ands_di_test2 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & 0xaaaaaaaaaaaaaaaall;
+
+  /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
+  /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+ands_di_test3 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & (b << 3);
+
+  /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+main ()
+{
+  int x;
+  s64 y;
+
+  x = ands_si_test1 (29, 4, 5);
+  if (x != 13)
+    abort ();
+
+  x = ands_si_test1 (5, 2, 20);
+  if (x != 25)
+    abort ();
+
+  x = ands_si_test2 (29, 4, 5);
+  if (x != 34)
+    abort ();
+
+  x = ands_si_test2 (1024, 2, 20);
+  if (x != 1044)
+    abort ();
+
+  x = ands_si_test3 (35, 4, 5);
+  if (x != 41)
+    abort ();
+
+  x = ands_si_test3 (5, 2, 20);
+  if (x != 25)
+    abort ();
+
+  y = ands_di_test1 (0x130000029ll,
+                     0x320000004ll,
+                     0x505050505ll);
+
+  if (y != ((0x130000029ll & 0x320000004ll) + 0x320000004ll + 0x505050505ll))
+    abort ();
+
+  y = ands_di_test1 (0x5000500050005ll,
+                     0x2111211121112ll,
+                     0x0000000002020ll);
+  if (y != 0x5000500052025ll)
+    abort ();
+
+  y = ands_di_test2 (0x130000029ll,
+                     0x320000004ll,
+                     0x505050505ll);
+  if (y != ((0x130000029ll & 0xaaaaaaaaaaaaaaaall) + 0x320000004ll + 0x505050505ll))
+    abort ();
+
+  y = ands_di_test2 (0x540004100ll,
+                     0x320000004ll,
+                     0x805050205ll);
+  if (y != (0x540004100ll + 0x805050205ll))
+    abort ();
+
+  y = ands_di_test3 (0x130000029ll,
+                     0x064000008ll,
+                     0x505050505ll);
+  if (y != ((0x130000029ll & (0x064000008ll << 3))
+	    + 0x064000008ll + 0x505050505ll))
+    abort ();
+
+  y = ands_di_test3 (0x130002900ll,
+                     0x088000008ll,
+                     0x505050505ll);
+  if (y != (0x130002900ll + 0x505050505ll))
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Index: gcc/testsuite/gcc.target/aarch64/ands.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/ands.c	(revision 0)
+++ gcc/testsuite/gcc.target/aarch64/ands.c	(revision 0)
@@ -0,0 +1,151 @@ 
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+ands_si_test1 (int a, int b, int c)
+{
+  int d = a & b;
+
+  /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+ands_si_test2 (int a, int b, int c)
+{
+  int d = a & 0xff;
+
+  /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, 255" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+ands_si_test3 (int a, int b, int c)
+{
+  int d = a & (b << 3);
+
+  /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+ands_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & b;
+
+  /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+ands_di_test2 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & 0xff;
+
+  /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, 255" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+ands_di_test3 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & (b << 3);
+
+  /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+main ()
+{
+  int x;
+  s64 y;
+
+  x = ands_si_test1 (29, 4, 5);
+  if (x != 13)
+    abort ();
+
+  x = ands_si_test1 (5, 2, 20);
+  if (x != 25)
+    abort ();
+
+  x = ands_si_test2 (29, 4, 5);
+  if (x != 38)
+    abort ();
+
+  x = ands_si_test2 (1024, 2, 20);
+  if (x != 1044)
+    abort ();
+
+  x = ands_si_test3 (35, 4, 5);
+  if (x != 41)
+    abort ();
+
+  x = ands_si_test3 (5, 2, 20);
+  if (x != 25)
+    abort ();
+
+  y = ands_di_test1 (0x130000029ll,
+                     0x320000004ll,
+                     0x505050505ll);
+
+  if (y != ((0x130000029ll & 0x320000004ll) + 0x320000004ll + 0x505050505ll))
+    abort ();
+
+  y = ands_di_test1 (0x5000500050005ll,
+                     0x2111211121112ll,
+                     0x0000000002020ll);
+  if (y != 0x5000500052025ll)
+    abort ();
+
+  y = ands_di_test2 (0x130000029ll,
+                     0x320000004ll,
+                     0x505050505ll);
+  if (y != ((0x130000029ll & 0xff) + 0x320000004ll + 0x505050505ll))
+    abort ();
+
+  y = ands_di_test2 (0x130002900ll,
+                     0x320000004ll,
+                     0x505050505ll);
+  if (y != (0x130002900ll + 0x505050505ll))
+    abort ();
+
+  y = ands_di_test3 (0x130000029ll,
+                     0x064000008ll,
+                     0x505050505ll);
+  if (y != ((0x130000029ll & (0x064000008ll << 3))
+	    + 0x064000008ll + 0x505050505ll))
+    abort ();
+
+  y = ands_di_test3 (0x130002900ll,
+                     0x088000008ll,
+                     0x505050505ll);
+  if (y != (0x130002900ll + 0x505050505ll))
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */