From patchwork Fri Apr 26 08:02:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuo-Jung Su X-Patchwork-Id: 239723 X-Patchwork-Delegate: agust@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3EDFF2C0104 for ; Fri, 26 Apr 2013 18:04:35 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0FD0C4A272; Fri, 26 Apr 2013 10:03:35 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VUWliSivV-ua; Fri, 26 Apr 2013 10:03:34 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 360094A0C1; Fri, 26 Apr 2013 10:02:29 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 649A94A0ED for ; Fri, 26 Apr 2013 10:02:18 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id X5XbVWPTevR6 for ; Fri, 26 Apr 2013 10:02:16 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pb0-f42.google.com (mail-pb0-f42.google.com [209.85.160.42]) by theia.denx.de (Postfix) with ESMTPS id 3A7EB4A0C1 for ; Fri, 26 Apr 2013 10:02:11 +0200 (CEST) Received: by mail-pb0-f42.google.com with SMTP id up7so1067927pbc.1 for ; Fri, 26 Apr 2013 01:02:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:in-reply-to:references; bh=W6nx0PR1JkyBZGs7D0JBQhGqd87sQ/fCwoSbfx8TFlg=; b=zhfn65smtw9h/xY13pENEAH2z18Jc/JBF0sWytDKJ80qM1KzX6E4VkSFRROm5H+ced P4aDASUKNlfee5gi7sUMWj+SpIATbKnHimBnJN0o0l9NMsAC9HkGGjecS6RXoPx1f9Q3 4e9AXPCBjonXu71Qc9wxUpSk9Ervc+dgUH/ijdyjPi/XUlDiYDEocrSDmKZTLVUqrHlv fzvQzcFyMzk7jJCqxJeqgyiHH3sCxAtfQ4Xw9P908PCGfwVxe6FOWWVFEjysaJQxSoFy fCV/n/Ahebm4kX1JK5cBefyTPKCSLpeGQGVt3nLNOSmqm+jQmSnTxrlhYmnp8zM+KDVO ZEfA== X-Received: by 10.68.13.168 with SMTP id i8mr57846885pbc.86.1366963330097; Fri, 26 Apr 2013 01:02:10 -0700 (PDT) Received: from localhost.localdomain ([220.132.37.35]) by mx.google.com with ESMTPSA id lo7sm11690140pab.19.2013.04.26.01.02.08 for (version=TLSv1 cipher=DES-CBC3-SHA bits=168/168); Fri, 26 Apr 2013 01:02:09 -0700 (PDT) From: Kuo-Jung Su To: u-boot@lists.denx.de Date: Fri, 26 Apr 2013 16:02:39 +0800 Message-Id: <1366963360-2987-11-git-send-email-dantesu@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1366963360-2987-1-git-send-email-dantesu@gmail.com> References: <1366963360-2987-1-git-send-email-dantesu@gmail.com> In-Reply-To: <1366277139-29728-2-git-send-email-dantesu@gmail.com> References: <1366277139-29728-2-git-send-email-dantesu@gmail.com> Cc: Kuo-Jung Su Subject: [U-Boot] [PATCH v3 10/11] video: add Faraday FTLCDC200 LCD controller support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Kuo-Jung Su Faraday FTLCDC200 Color LCD controller performs translation of pixel-coded data into the required formats and timings to drive a variety of single/dual mono and color LCDs. Depending on the LCD type and mode, the unpacked data can represent: 1. an actual true display gray or color value 2. an address to a 256 x 16 bit wide palette RAM gray or color value. The FTLCDC200 generates 4 individual interrupts for: 1. DMA FIFO underflow 2. base address update 3. vertical status 4. bus error. There is also a single combined interrupt that is raised when any of the individual interrupts become active. Signed-off-by: Kuo-Jung Su CC: Anatolij Gustschin Acked-by: Anatolij Gustschin --- drivers/video/Makefile | 1 + drivers/video/ftlcdc200.c | 144 +++++++++++++++++++++++++++ drivers/video/ftlcdc200_panel.c | 210 +++++++++++++++++++++++++++++++++++++++ include/faraday/ftlcdc200.h | 179 +++++++++++++++++++++++++++++++++ include/lcd.h | 33 ++++++ 5 files changed, 567 insertions(+) create mode 100644 drivers/video/ftlcdc200.c create mode 100644 drivers/video/ftlcdc200_panel.c create mode 100644 include/faraday/ftlcdc200.h diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 53952ab..ec8df26 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -35,6 +35,7 @@ COBJS-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \ exynos_mipi_dsi_lowlevel.o COBJS-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o +COBJS-$(CONFIG_FTLCDC200) += ftlcdc200.o ftlcdc200_panel.o COBJS-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o COBJS-$(CONFIG_PXA_LCD) += pxa_lcd.o COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o diff --git a/drivers/video/ftlcdc200.c b/drivers/video/ftlcdc200.c new file mode 100644 index 0000000..a9c1198 --- /dev/null +++ b/drivers/video/ftlcdc200.c @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2010 + * Faraday Technology Inc. + * Kuo-Jung Su + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +static struct ftlcdc200_regs __iomem *regs + = (void __iomem *)CONFIG_FTLCDC200_BASE; + +static void ftlcdc2xx_fixup(struct vidinfo *panel) +{ + u_long ht, vt; + u_long div, clk; + long fps = 60; + long upper = 32767; + long lower = -32767; + + if (panel->vl_fps) + return; + + /* If it's serial mode */ + if (panel->vl_serial & SPPR_SERIAL) + clk = clk_get_rate("AHB") / 3; + else + clk = clk_get_rate("AHB"); + + /* Derive clock divisor */ + ht = panel->vl_col + panel->vl_hbp + panel->vl_hfp + panel->vl_hsw; + vt = panel->vl_row + panel->vl_vbp + panel->vl_vfp + panel->vl_vsw; + for (div = 1; div <= 0x7f; ++div) { + long tmp = (clk / div / ht / vt); + if (fps > tmp) { + lower = tmp; + break; + } + upper = tmp; + } + if ((upper - fps) > (fps - lower)) + div += 1; + div = (div > 1) ? (div - 1) : div; + + /* Update hardware register cache */ + panel->vl_polarity = (panel->vl_polarity & (~0x7f00)) + | ((div - 1) << 8); + + /* Derive real frame rate */ + panel->vl_fps = (u_long)(clk / div / ht / vt); + + debug("ftlcdc200: %s\n", panel->vl_name); + debug("ftlcdc200: fps=%u (%u < FPS < %u)\n", + (unsigned int)panel->vl_fps, + (unsigned int)lower, + (unsigned int)upper); + debug("ftlcdc200: div=%u (ahb=%u MHz)\n", + (unsigned int)div, + (unsigned int)clk_get_rate("AHB") / 1000000); +} + +/* setcolreg used in 8bpp/16bpp */ +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ + /* nothing needs to be done, we use true color */ +} + +/* initcolregs used in monochrome */ +void lcd_initcolregs(void) +{ + /* nothing needs to be done, we use true color */ +} + +void lcd_ctrl_init(void *lcdbase) +{ + uint32_t i, v; + + /* + * initialize the contrast lookup table and the Red, Green, Blue + * gamma lookup table, fill the straight line x-y=0 to the contrast + * and gamma lookup table + */ + for (i = 0; i < 64; i++) { + v = 0x03020100 + 0x04040404 * i; + writel(v, ®s->gamma_r[i]); + writel(v, ®s->gamma_g[i]); + writel(v, ®s->gamma_b[i]); + } + + writel(virt_to_phys(lcdbase), ®s->fb0); + + debug("ftlcdc200: fb_base=0x%08X@0x%08X\n", + (uint32_t)lcdbase, readl(®s->fb0)); +} + +void lcd_enable(void) +{ + struct vidinfo *panel = &panel_info; + + /* 1. derive the clock parameters at runtime */ + ftlcdc2xx_fixup(panel); + /* 2. disable lcd */ + writel(0, ®s->fer); + /* 3. setup panel parameters */ + writel(panel->vl_pixel, ®s->ppr); + writel(HTCR_PL(panel->vl_col) | HTCR_HSYNC(panel->vl_hsw) + | HTCR_HBP(panel->vl_hbp) | HTCR_HFP(panel->vl_hfp), + ®s->htcr); + writel(VTCR0_LF(panel->vl_row) | VTCR0_VSYNC(panel->vl_vsw) + | VTCR0_VFP(panel->vl_vfp), ®s->vtcr[0]); + writel(VTCR1_VBP(panel->vl_vbp), ®s->vtcr[1]); + writel(panel->vl_polarity, ®s->pcr); + writel(panel->vl_serial, ®s->sppr); + writel(panel->vl_ccir656, ®s->ccir); + /* 4. default 4 cycles delay for all framebuffer */ + writel(0x04040404, ®s->fifo); + /* 5. disable & clean interrupts */ + writel(0x00, ®s->ier); + writel(0x0f, ®s->iscr); + /* 6. enable lcd */ + writel(panel->vl_enable, ®s->fer); +} + +ulong calc_fbsize(void) +{ + return ((panel_info.vl_col * panel_info.vl_row * + NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE; +} diff --git a/drivers/video/ftlcdc200_panel.c b/drivers/video/ftlcdc200_panel.c new file mode 100644 index 0000000..ca1a091 --- /dev/null +++ b/drivers/video/ftlcdc200_panel.c @@ -0,0 +1,210 @@ +/* + * Faraday LCD Controller + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#include +#include +#include +#include + +struct vidinfo panel_info = { +#if defined(CONFIG_FTLCDC200_320X240P_SHARP) + .vl_name = "SHARP-320x240p", + .vl_col = 320, + .vl_row = 240, + .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */ + .vl_fps = 0, /* drived at runtime */ + .vl_hsw = 0x10, + .vl_hfp = 0x01, + .vl_hbp = 0x10, + .vl_vsw = 0x01, + .vl_vfp = 0x0f, + .vl_vbp = 0x07, + .vl_enable = FER_EN | FER_ON, + .vl_pixel = PPR_BPP_16 | PPR_PWROFF | PPR_BGR | PPR_ENDIAN_LBLP, + .vl_polarity = POL_DIV(23) | POL_IHS | POL_ICK, + .vl_serial = 0, + .vl_ccir656 = 0, +#elif defined(CONFIG_FTLCDC200_320X240P_AUO) + .vl_name = "AUO-320x240p", + .vl_col = 320, + .vl_row = 240, + .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */ + .vl_fps = 0, /* drived at runtime */ + .vl_hsw = 0x17, + .vl_hfp = 0x01, + .vl_hbp = 0x2A, + .vl_vsw = 0x01, + .vl_vfp = 0x01, + .vl_vbp = 0x0D, + .vl_enable = FER_EN | FER_ON, + .vl_pixel = PPR_PWROFF, + .vl_polarity = POL_DIV(21) | POL_IHS, + .vl_serial = 0, + .vl_ccir656 = 0, +#elif defined(CONFIG_FTLCDC200_320X240S_AUO) + .vl_name = "AUO-320x240s", + .vl_col = 320, + .vl_row = 240, + .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */ + .vl_fps = 0, /* drived at runtime */ + .vl_hsw = 0x17, + .vl_hfp = 0x01, + .vl_hbp = 0x2A, + .vl_vsw = 0x01, + .vl_vfp = 0x01, + .vl_vbp = 0x0D, + .vl_enable = FER_EN | FER_ON, + .vl_pixel = PPR_BPP_16 | PPR_PWROFF | PPR_PANEL_8BIT + | PPR_ENDIAN_LBBP, + .vl_polarity = POL_DIV(7) | POL_IHS, + .vl_serial = SPPR_SERIAL | SPPR_CS(1), + .vl_ccir656 = 0, +#elif defined(CONFIG_FTLCDC200_640X480P_PV) + .vl_name = "PV-640x480p", + .vl_col = 640, + .vl_row = 480, + .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */ + .vl_fps = 0, /* drived at runtime */ + .vl_hsw = 0x63, + .vl_hfp = 0x01, + .vl_hbp = 0x2D, + .vl_vsw = 0x44, + .vl_vfp = 0x01, + .vl_vbp = 0x1D, + .vl_enable = FER_EN | FER_ON, + .vl_pixel = PPR_BPP_16 | PPR_PWROFF | PPR_BGR | PPR_ENDIAN_LBBP, + .vl_polarity = POL_DIV(6) | POL_IHS | POL_IVS | POL_ICK, + .vl_serial = 0, + .vl_ccir656 = 0, +#elif defined(CONFIG_FTLCDC200_800X480S_TPO) + .vl_name = "TPO-800x480s", + .vl_col = 800, + .vl_row = 480, + .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */ + .vl_fps = 0, /* drived at runtime */ + .vl_hsw = 0x01, + .vl_hfp = 0x2C, + .vl_hbp = 0x01, + .vl_vsw = 0x01, + .vl_vfp = 0x01, + .vl_vbp = 0x01, + .vl_enable = FER_EN | FER_ON, + .vl_pixel = PPR_BPP_16 | PPR_PWROFF | PPR_ENDIAN_LBBP, + .vl_polarity = POL_DIV(1) | POL_IHS | POL_IVS | POL_ICK, + .vl_serial = SPPR_SERIAL | SPPR_CS(0), + .vl_ccir656 = 0, +#elif defined(CONFIG_FTLCDC200_800X480P_TPO) + .vl_name = "TPO-800x480p", + .vl_col = 800, + .vl_row = 480, + .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */ + .vl_fps = 0, /* drived at runtime */ + .vl_hsw = 0x04, + .vl_hfp = 0x2C, + .vl_hbp = 0xD4, + .vl_vsw = 0x02, + .vl_vfp = 0x0A, + .vl_vbp = 0x22, + .vl_enable = FER_EN | FER_ON, + .vl_pixel = PPR_BPP_16 | PPR_PWROFF | PPR_BGR | PPR_ENDIAN_LBBP, + .vl_polarity = POL_DIV(7) | POL_IHS | POL_IVS | POL_ICK, + .vl_serial = 0, + .vl_ccir656 = 0, +#elif defined(CONFIG_FTLCDC200_800X480P_CPT) + /* Chunghwa Picture Tubes - CLAA048LA0BCT */ + .vl_name = "CPT-800x480p", + .vl_col = 800, + .vl_row = 480, + .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */ + .vl_fps = 0, /* drived at runtime */ + .vl_hsw = 0x01, + .vl_hfp = 0x32, + .vl_hbp = 0x31, + .vl_vsw = 0x01, + .vl_vfp = 0x0E, + .vl_vbp = 0x05, + .vl_enable = FER_EN | FER_ON, + .vl_pixel = PPR_BPP_16 | PPR_PWROFF | PPR_PANEL_8BIT + | PPR_ENDIAN_LBBP, + .vl_polarity = POL_DIV(7) | POL_IHS | POL_IVS | POL_ICK, + .vl_serial = 0, + .vl_ccir656 = 0, +#elif defined(CONFIG_FTLCDC200_800X600_VGA) + .vl_name = "D-SUB: VGA-800x600", + .vl_col = 800, + .vl_row = 600, + .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */ + .vl_fps = 0, /* drived at runtime */ + .vl_hsw = 0x7E, + .vl_hfp = 0x26, + .vl_hbp = 0x56, + .vl_vsw = 0x02, + .vl_vfp = 0x01, + .vl_vbp = 0x16, + .vl_enable = FER_EN | FER_ON, + .vl_pixel = PPR_PANEL_8BIT | PPR_BPP_16, + .vl_polarity = POL_DIV(3) | POL_IVS | POL_IHS, + .vl_serial = 0, + .vl_ccir656 = 0, +#elif defined(CONFIG_FTLCDC200_1024X768_VGA) + .vl_name = "D-SUB: VGA-1024x768", + .vl_col = 1024, + .vl_row = 768, + .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */ + .vl_fps = 0, /* drived at runtime */ + .vl_hsw = 0x7E, + .vl_hfp = 0x26, + .vl_hbp = 0x56, + .vl_vsw = 0x02, + .vl_vfp = 0x01, + .vl_vbp = 0x16, + .vl_enable = FER_EN | FER_ON, + .vl_pixel = PPR_PANEL_8BIT | PPR_BPP_16, + .vl_polarity = POL_DIV(2) | POL_IVS | POL_IHS, + .vl_serial = 0, + .vl_ccir656 = 0, +#elif defined(CONFIG_FTLCDC200_720X480_NTSC) + .vl_name = "A/V: NTSC-720x480", + .vl_col = 720, + .vl_row = 480, + .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */ + .vl_fps = 30, /* Frame per second */ + .vl_hsw = 0x06, + .vl_hfp = 0x7D, + .vl_hbp = 0x01, + .vl_vsw = 0x0F, + .vl_vfp = 0x01, + .vl_vbp = 0x1A, + .vl_enable = FER_EN | FER_ON, + .vl_pixel = PPR_BPP_16 | PPR_PWROFF | PPR_ENDIAN_LBBP, + .vl_polarity = 0, + .vl_serial = 0, + .vl_ccir656 = 3, +#elif defined(CONFIG_FTLCDC200_640X480_NTSC) + .vl_name = "A/V: NTSC-640x480", + .vl_col = 640, + .vl_row = 480, + .vl_bpix = 4, /* Bits per pixel, 0 = 1, ... 4 = 16 */ + .vl_fps = 30, /* Frame per second */ + .vl_hsw = 0x02, + .vl_hfp = 0xD1, + .vl_hbp = 0x01, + .vl_vsw = 0x10, + .vl_vfp = 0x01, + .vl_vbp = 0x19, + .vl_enable = FER_EN | FER_ON, + .vl_pixel = PPR_BPP_16 | PPR_PWROFF | PPR_ENDIAN_LBBP, + .vl_polarity = 0, + .vl_serial = 0, + .vl_ccir656 = 1, +#else +#error "Please specific target LCD panel." +#endif +}; diff --git a/include/faraday/ftlcdc200.h b/include/faraday/ftlcdc200.h new file mode 100644 index 0000000..9d7cc33 --- /dev/null +++ b/include/faraday/ftlcdc200.h @@ -0,0 +1,179 @@ +/* + * Faraday LCD Controller + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef __FTLCDC200_H +#define __FTLCDC200_H + +/* FTLCDC200 Registers */ +struct ftlcdc200_regs { + /* 0x000 ~ 0x0ff */ + uint32_t fer; /* 0x000: Function Enable Register */ + uint32_t ppr; /* 0x004: Panel Pixel Register */ + uint32_t ier; /* 0x008: Interrupt Enable Register */ + uint32_t iscr; /* 0x00C: Interrupt Status Clear Register */ + uint32_t isr; /* 0x010: Interrupt Status Register */ + uint32_t rsvd0[1]; + uint32_t fb0; /* 0x018: Framebuffer Base Register 0 */ + uint32_t rsvd1[2]; + uint32_t fb1; /* 0x024: Framebuffer Base Register 1 */ + uint32_t rsvd2[2]; + uint32_t fb2; /* 0x030: Framebuffer Base Register 2 */ + uint32_t rsvd3[2]; + uint32_t fb3; /* 0x03C: Framebuffer Base Register 3 */ + uint32_t rsvd4[2]; + uint32_t patg; /* 0x048: Pattern Generator */ + uint32_t fifo; /* 0x04C: FIFO Threshold */ + uint32_t gpio; /* 0x050: GPIO */ + uint32_t rsvd5[43]; + + /* 0x100 ~ 0x1ff */ + uint32_t htcr; /* Horizontal Timing Control Register */ + uint32_t vtcr[2]; /* Vertical Timing Control Register */ + uint32_t pcr; /* Polarity Control Register */ + uint32_t rsvd6[60]; + + /* 0x200 ~ 0x2ff */ + uint32_t sppr; /* Serial Panel Pixel Register */ + uint32_t ccir; /* CCIR565 Register */ + uint32_t rsvd7[62]; + + /* 0x300 ~ 0x3ff */ + uint32_t pipr; /* Picture-In-Picture Register */ + uint32_t pip1pos; /* Sub-picture 1 position */ + uint32_t pip1dim; /* Sub-picture 1 dimension */ + uint32_t pip2pos; /* Sub-picture 2 position */ + uint32_t pip2dim; /* Sub-picture 2 dimension */ + uint32_t rsvd8[59]; + + /* 0x400 ~ 0x5ff */ + uint32_t cmnt[4]; /* Color Management */ + uint32_t rsvd9[124]; + + /* 0x600 ~ 0x6ff */ + uint32_t gamma_r[64]; /* RED - Gamma Correct */ + + /* 0x700 ~ 0x7ff */ + uint32_t gamma_g[64]; /* GREEN - Gamma Correct */ + + /* 0x800 ~ 0x8ff */ + uint32_t gamma_b[64]; /* BLUE - Gamma Correct */ + + /* 0x900 ~ 0x9ff */ + uint32_t rsvd10[64]; + + /* 0xa00 ~ 0xbff */ + uint32_t palette[128]; /* Palette Write Port */ + + /* 0xc00 ~ 0xcff */ + uint32_t cstn_cr; /* CSTN Control Register */ + uint32_t cstn_pr; /* CSTN Parameter Register */ + uint32_t rsvd11[62]; + + /* 0xd00 ~ 0xdff */ + uint32_t cstn_bmap[16]; /* CSTN bitmap write port */ + uint32_t rsvd12[48]; +}; + +/* LCD Function Enable Register */ +#define FER_EN (1 << 0) /* chip enabled */ +#define FER_ON (1 << 1) /* screen on */ +#define FER_YUV420 (3 << 2) +#define FER_YUV422 (2 << 2) +#define FER_YUV (1 << 3) /* 1:YUV, 0:RGB */ + +/* LCD Panel Pixel Register */ +#define PPR_BPP_1 (0 << 0) +#define PPR_BPP_2 (1 << 0) +#define PPR_BPP_4 (2 << 0) +#define PPR_BPP_8 (3 << 0) +#define PPR_BPP_16 (4 << 0) +#define PPR_BPP_24 (5 << 0) +#define PPR_BPP_MASK (7 << 0) +#define PPR_PWROFF (1 << 3) +#define PPR_BGR (1 << 4) +#define PPR_ENDIAN_LBLP (0 << 5) +#define PPR_ENDIAN_BBBP (1 << 5) +#define PPR_ENDIAN_LBBP (2 << 5) +#define PPR_ENDIAN_MASK (3 << 5) +#define PPR_RGB1 (PPR_BPP_1) +#define PPR_RGB2 (PPR_BPP_2) +#define PPR_RGB4 (PPR_BPP_4) +#define PPR_RGB8 (PPR_BPP_8) +#define PPR_RGB12 (PPR_BPP_16 | (2 << 7)) +#define PPR_RGB16_555 (PPR_BPP_16 | (1 << 7)) +#define PPR_RGB16_565 (PPR_BPP_16 | (0 << 7)) +#define PPR_RGB24 (PPR_BPP_24) +#define PPR_RGB32 (PPR_BPP_24) +#define PPR_RGB_MASK (PPR_BPP_MASK | (3 << 7)) +#define PPR_VCOMP_VSYNC (0 << 9) +#define PPR_VCOMP_VBP (1 << 9) +#define PPR_VCOMP_VAIMG (2 << 9) +#define PPR_VCOMP_VFP (3 << 9) +#define PPR_VCOMP_MASK (3 << 9) +#define PPR_PANEL_6BIT (0 << 11) +#define PPR_PANEL_8BIT (1 << 11) +#define PPR_DITHER565 (0 << 12) +#define PPR_DITHER555 (1 << 12) +#define PPR_DITHER444 (2 << 12) +#define PPR_HCLK_RESET (1 << 14) +#define PPR_LCCLK_RESET (1 << 15) + +/* LCD Interrupt Enable Register */ +#define IER_FIFOUR (1 << 0) +#define IER_NEXTFB (1 << 1) +#define IER_VCOMP (1 << 2) +#define IER_BUSERR (1 << 3) + +/* LCD Interrupt Status Register */ +#define ISR_FIFOUR (1 << 0) +#define ISR_NEXTFB (1 << 1) +#define ISR_VCOMP (1 << 2) +#define ISR_BUSERR (1 << 3) + +/* LCD Horizontal Timing Control Register */ +#define HTCR_HBP(x) ((((x) - 1) & 0xff) << 24) +#define HTCR_HFP(x) ((((x) - 1) & 0xff) << 16) +#define HTCR_HSYNC(x) ((((x) - 1) & 0xff) << 8) +#define HTCR_PL(x) (((x >> 4) - 1) & 0xff) + +/* LCD Vertical Timing Control Register 0 */ +#define VTCR0_VFP(x) (((x) & 0xff) << 24) +#define VTCR0_VSYNC(x) ((((x) - 1) & 0x3f) << 16) +#define VTCR0_LF(x) (((x) - 1) & 0xfff) + +/* LCD Vertical Timing Control Register 1 */ +#define VTCR1_VBP(x) ((x) & 0xff) + +/* LCD Polarity Control Register */ +#define POL_IVS (1 << 0) +#define POL_IHS (1 << 1) +#define POL_ICK (1 << 2) +#define POL_IDE (1 << 3) +#define POL_IPWR (1 << 4) +#define POL_DIV(x) ((((x) - 1) & 0x7f) << 8) + +/* LCD Serial Panel Pixel Register */ +#define SPPR_SERIAL (1 << 0) +#define SPPR_DELTA (1 << 1) +#define SPPR_CS(x) ((x) << 2) +#define SPPR_CS_RGB (0 << 2) +#define SPPR_CS_BRG (1 << 2) +#define SPPR_CS_GBR (2 << 2) +#define SPPR_LSR (1 << 4) +#define SPPR_AUO052 (1 << 5) + +/* LCD CCIR656 Register */ +#define CCIR_PAL (0 << 0) +#define CCIR_NTSC (1 << 0) +#define CCIR_P640 (0 << 1) +#define CCIR_P720 (1 << 1) +#define CCIR_PHASE(x) ((x) << 2) + +#endif /* __FTLCDC200_H */ diff --git a/include/lcd.h b/include/lcd.h index c6e7fc5..1d9e584 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -253,6 +253,39 @@ typedef struct vidinfo { void init_panel_info(vidinfo_t *vid); +#elif defined(CONFIG_FTLCDC200) + +typedef struct vidinfo { + ushort vl_col; /* Number of columns (i.e. 800) */ + ushort vl_row; /* Number of rows (i.e. 600) */ + + u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2 ... 4 = 16 */ + + /* Timing Parameters */ + u_char vl_fps; /* Frame per second */ + + u_char vl_hsw; + u_char vl_hbp; + u_char vl_hfp; + + u_char vl_vsw; + u_char vl_vbp; + u_char vl_vfp; + + /* Pre-defined FTLCDC200 register values */ + u_long vl_enable; /* LCDEnable */ + u_long vl_pixel; /* PanelPixel */ + u_long vl_polarity;/* Polarity */ + u_long vl_serial; /* SerialPanelPixel */ + u_long vl_ccir656; /* CCIR656 */ + + /* Panel name */ + char *vl_name; + + ushort *cmap; /* Pointer to the colormap */ + void *priv; /* Pointer to driver-specific data */ +} vidinfo_t; + #else typedef struct vidinfo {