From patchwork Fri Apr 26 08:02:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuo-Jung Su X-Patchwork-Id: 239716 X-Patchwork-Delegate: hs@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id E5CC72C0106 for ; Fri, 26 Apr 2013 18:02:46 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B3CDE4A109; Fri, 26 Apr 2013 10:02:40 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nTCzE49jkMjC; Fri, 26 Apr 2013 10:02:40 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BA6614A10B; Fri, 26 Apr 2013 10:02:20 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D67224A112 for ; Fri, 26 Apr 2013 10:02:06 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id C1KdFQkbGSRL for ; Fri, 26 Apr 2013 10:02:05 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pd0-f178.google.com (mail-pd0-f178.google.com [209.85.192.178]) by theia.denx.de (Postfix) with ESMTPS id 7E6024A0ED for ; Fri, 26 Apr 2013 10:01:51 +0200 (CEST) Received: by mail-pd0-f178.google.com with SMTP id w11so309369pde.9 for ; Fri, 26 Apr 2013 01:01:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:in-reply-to:references; bh=WEZIiuyzdebcWksUmtDPSU2k8U+SQc16QvqIWcjgZRw=; b=K6cJOrRr66CVAXjqccVXXCkuicCDtGyztD8JzEH4qKhrVJgXqIO0UQ1HI4eCatMRxU PLs73KNHmTfa4FYnISPiegakbxGcqa3iC0/P2GgCxeajGC9TjMcY2RT47Dd8hPybeOBa vgCbpJOyOAz85Arhj/BEe40BAlNPUHCwmdcQgPuz01C478B5nH5qLoghN7KIQ7Cf1Zc+ NugHXhp3UFNNu4c/3OdprYZWGypfulKe8vXiyPqCQN/URe/cZ2N/cn4kzoNSyUT1j/Vn 4OyV5ueNUIbE3Jx4EweYxPm3TyQcO4lGl59HQGWYhFZ4KIEIFKmRLKkdFoLQ/uVYS0pd 7/Ww== X-Received: by 10.68.32.198 with SMTP id l6mr57740178pbi.187.1366963309944; Fri, 26 Apr 2013 01:01:49 -0700 (PDT) Received: from localhost.localdomain ([220.132.37.35]) by mx.google.com with ESMTPSA id lo7sm11690140pab.19.2013.04.26.01.01.47 for (version=TLSv1 cipher=DES-CBC3-SHA bits=168/168); Fri, 26 Apr 2013 01:01:49 -0700 (PDT) From: Kuo-Jung Su To: u-boot@lists.denx.de Date: Fri, 26 Apr 2013 16:02:33 +0800 Message-Id: <1366963360-2987-5-git-send-email-dantesu@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1366963360-2987-1-git-send-email-dantesu@gmail.com> References: <1366963360-2987-1-git-send-email-dantesu@gmail.com> In-Reply-To: <1366277139-29728-2-git-send-email-dantesu@gmail.com> References: <1366277139-29728-2-git-send-email-dantesu@gmail.com> Cc: Heiko Schocher , Kuo-Jung Su Subject: [U-Boot] [PATCH v3 04/11] i2c: add Faraday FTI2C010 I2C controller support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Kuo-Jung Su Faraday FTI2C010 is a multi-function I2C controller which supports both master and slave mode. This patch simplily implements the master mode only. Signed-off-by: Kuo-Jung Su CC: Heiko Schocher Acked-by: Heiko Schocher --- drivers/i2c/Makefile | 1 + drivers/i2c/fti2c010.c | 360 ++++++++++++++++++++++++++++++++++++++++++++++++ drivers/i2c/fti2c010.h | 71 ++++++++++ 3 files changed, 432 insertions(+) create mode 100644 drivers/i2c/fti2c010.c create mode 100644 drivers/i2c/fti2c010.h diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 5dbdbe3..ed2b8c0 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -29,6 +29,7 @@ COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o COBJS-$(CONFIG_DW_I2C) += designware_i2c.o COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o +COBJS-$(CONFIG_FTI2C010) += fti2c010.o COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o COBJS-$(CONFIG_I2C_MV) += mv_i2c.o COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c new file mode 100644 index 0000000..52a46bf --- /dev/null +++ b/drivers/i2c/fti2c010.c @@ -0,0 +1,360 @@ +/* + * Faraday I2C Controller + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#include +#include +#include + +#include "fti2c010.h" + +#define I2C_RD 1 +#define I2C_WR 0 + +struct fti2c010_chip { + void __iomem *regs; + uint32_t bus; + uint32_t speed; +}; + +#if defined(CONFIG_HARD_I2C) + +static struct fti2c010_chip chip_list[] = { +#ifdef CONFIG_I2C_MULTI_BUS +# ifdef CONFIG_FTI2C010_BASE + { + .bus = 0, + .speed = 0, + .regs = (void __iomem *)CONFIG_FTI2C010_BASE, + }, +# endif +# ifdef CONFIG_FTI2C010_BASE1 + { + .bus = 1, + .speed = 0, + .regs = (void __iomem *)CONFIG_FTI2C010_BASE1, + }, +# endif +# ifdef CONFIG_FTI2C010_BASE2 + { + .bus = 2, + .speed = 0, + .regs = (void __iomem *)CONFIG_FTI2C010_BASE2, + }, +# endif +# ifdef CONFIG_FTI2C010_BASE3 + { + .bus = 3, + .speed = 0, + .regs = (void __iomem *)CONFIG_FTI2C010_BASE3, + }, +# endif +#else /* #ifdef CONFIG_I2C_MULTI_BUS */ + { + .bus = 0, + .speed = 0, + .regs = (void __iomem *)CONFIG_FTI2C010_BASE, + }, +#endif /* #ifdef CONFIG_I2C_MULTI_BUS */ +}; + +static struct fti2c010_chip *priv = chip_list; + +static int fti2c010_wait(uint32_t mask) +{ + int ret = -1; + uint32_t stat, t; + struct fti2c010_regs __iomem *regs = priv->regs; + + for (t = get_timer(0); get_timer(t) < 100; ) { + stat = readl(®s->sr); + if ((stat & mask) == mask) { + ret = 0; + break; + } + } + + return ret; +} + +/* + * u-boot I2C API + */ + +/* + * Initialization, must be called once on start up, may be called + * repeatedly to change the speed and slave addresses. + */ +void i2c_init(int speed, int slaveaddr) +{ + if (speed || priv->speed == 0) + i2c_set_bus_speed(speed); +} + +/* + * Probe the given I2C chip address. Returns 0 if a chip responded, + * not 0 on failure. + */ +int i2c_probe(uchar chip) +{ + int rc; + struct fti2c010_regs __iomem *regs = priv->regs; + + i2c_init(0, chip); + + /* 1. Select slave device (7bits Address + 1bit R/W) */ + writel((chip << 1) + I2C_WR, ®s->dr); + writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr); + rc = fti2c010_wait(SR_DT); + if (rc) + return rc; + + /* 2. Select device register */ + writel(0, ®s->dr); + writel(CR_ENABLE | CR_TBEN, ®s->cr); + rc = fti2c010_wait(SR_DT); + + return rc; +} + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int rc, pos; + uchar paddr[4]; + struct fti2c010_regs __iomem *regs = priv->regs; + + i2c_init(0, chip); + + paddr[0] = (addr >> 0) & 0xFF; + paddr[1] = (addr >> 8) & 0xFF; + paddr[2] = (addr >> 16) & 0xFF; + paddr[3] = (addr >> 24) & 0xFF; + + /* + * Phase A. Set register address + */ + + /* A.1 Select slave device (7bits Address + 1bit R/W) */ + writel((chip << 1) + I2C_WR, ®s->dr); + writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr); + rc = fti2c010_wait(SR_DT); + if (rc) + return rc; + + /* A.2 Select device register */ + for (pos = 0; pos < alen; ++pos) { + uint32_t ctrl = CR_ENABLE | CR_TBEN; + writel(paddr[pos], ®s->dr); + writel(ctrl, ®s->cr); + rc = fti2c010_wait(SR_DT); + if (rc) + return rc; + } + + /* + * Phase B. Get register data + */ + + /* B.1 Select slave device (7bits Address + 1bit R/W) */ + writel((chip << 1) + I2C_RD, ®s->dr); + writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr); + rc = fti2c010_wait(SR_DT); + if (rc) + return rc; + + /* B.2 Get register data */ + for (pos = 0; pos < len; ++pos) { + uint32_t ctrl = CR_ENABLE | CR_TBEN; + uint32_t stat = SR_DR; + if (pos == len - 1) { + ctrl |= CR_NAK | CR_STOP; + stat |= SR_ACK; + } + writel(ctrl, ®s->cr); + rc = fti2c010_wait(stat); + if (rc) + break; + buf[pos] = (uchar)(readl(®s->dr) & 0xFF); + } + + return rc; +} + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int rc, pos; + uchar paddr[4]; + struct fti2c010_regs __iomem *regs = priv->regs; + + i2c_init(0, chip); + + paddr[0] = (addr >> 0) & 0xFF; + paddr[1] = (addr >> 8) & 0xFF; + paddr[2] = (addr >> 16) & 0xFF; + paddr[3] = (addr >> 24) & 0xFF; + + /* + * Phase A. Set register address + */ + + /* A.1 Select slave device (7bits Address + 1bit R/W) */ + writel((chip << 1) + I2C_WR, ®s->dr); + writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr); + rc = fti2c010_wait(SR_DT); + if (rc) + return rc; + + /* A.2 Select device register */ + for (pos = 0; pos < alen; ++pos) { + uint32_t ctrl = CR_ENABLE | CR_TBEN; + writel(paddr[pos], ®s->dr); + writel(ctrl, ®s->cr); + rc = fti2c010_wait(SR_DT); + if (rc) + return rc; + } + + /* + * Phase B. Set register data + */ + + for (pos = 0; pos < len; ++pos) { + uint32_t ctrl = CR_ENABLE | CR_TBEN; + if (pos == len - 1) + ctrl |= CR_STOP; + writel(buf[pos], ®s->dr); + writel(ctrl, ®s->cr); + rc = fti2c010_wait(SR_DT); + if (rc) + break; + } + + return rc; +} + +/* + * Functions for setting the current I2C bus and its speed + */ +#ifdef CONFIG_I2C_MULTI_BUS + +/* + * i2c_set_bus_num: + * + * Change the active I2C bus. Subsequent read/write calls will + * go to this one. + * + * bus - bus index, zero based + * + * Returns: 0 on success, not 0 on failure + * + */ +int i2c_set_bus_num(unsigned int bus) +{ + if (bus >= sizeof(chip_list) / sizeof(chip_list[0])) + return -1; + priv = chip_list + bus; + i2c_init(5000, 0); + return 0; +} + +/* + * i2c_get_bus_num: + * + * Returns index of currently active I2C bus. Zero-based. + */ + +unsigned int i2c_get_bus_num(void) +{ + return priv->bus; +} + +#endif /* #ifdef CONFIG_I2C_MULTI_BUS */ + +/* + * i2c_set_bus_speed: + * + * Change the speed of the active I2C bus + * + * speed - bus speed in Hz + * + * Returns: 0 on success, not 0 on failure + * + */ +int i2c_set_bus_speed(unsigned int speed) +{ + struct fti2c010_regs __iomem *regs = priv->regs; +#ifdef CONFIG_FTI2C010_SCLK + ulong apb = CONFIG_FTI2C010_SCLK; +#else + ulong apb = clk_get_rate("I2C"); +#endif + ulong div = 0x640; + ulong gsr = 0; + ulong tsr = 0x20; + ulong ts; + + writel(BIT_MASK(0), ®s->cr); + for (ts = get_timer(0); get_timer(ts) < 100; ) { + if (!(readl(®s->cr) & BIT_MASK(0))) + break; + } + + /* SCLout = PCLK/(2*(COUNT + 2) + GSR) */ + priv->speed = apb / (2 * (div + 2) + gsr); + + if (speed > 0) { + for (div = 0; div < 0x1000000; ++div) { + priv->speed = apb / (2 * (div + 2) + gsr); + if (priv->speed < speed) + break; + } + } + + writel((gsr << 10) | tsr, ®s->tgsr); + writel(div, ®s->cdr); + + return 0; +} + +/* + * i2c_get_bus_speed: + * + * Returns speed of currently active I2C bus in Hz + */ + +unsigned int i2c_get_bus_speed(void) +{ + return priv->speed; +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/drivers/i2c/fti2c010.h b/drivers/i2c/fti2c010.h new file mode 100644 index 0000000..214f55a --- /dev/null +++ b/drivers/i2c/fti2c010.h @@ -0,0 +1,71 @@ +/* + * Faraday I2C Controller + * + * (C) Copyright 2010 Faraday Technology + * Dante Su + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef _FTI2C010_H +#define _FTI2C010_H + +/* + * FTI2C010 registers + */ +struct fti2c010_regs { + uint32_t cr; /* 0x00: control register */ + uint32_t sr; /* 0x04: status register */ + uint32_t cdr; /* 0x08: clock division register */ + uint32_t dr; /* 0x0c: data register */ + uint32_t sar; /* 0x10: slave address register */ + uint32_t tgsr;/* 0x14: time & glitch suppression register */ + uint32_t bmr; /* 0x18: bus monitor register */ + uint32_t rsvd[5]; + uint32_t revr;/* 0x30: revision register */ +}; + +/* + * REG_CTRL + */ +#define CR_ALIEN 0x2000 /* Arbitration lose */ +#define CR_SAMIEN 0x1000 /* slave address match */ +#define CR_STOPIEN 0x800 /* stop condition */ +#define CR_BERRIEN 0x400 /* non ACK response */ +#define CR_DRIEN 0x200 /* data receive */ +#define CR_DTIEN 0x100 /* data transmit */ +#define CR_TBEN 0x80 /* transfer byte enable */ +#define CR_NAK 0x40 /* NACK */ +#define CR_STOP 0x20 /* stop */ +#define CR_START 0x10 /* start */ +#define CR_GCEN 0x8 /* general call */ +#define CR_SCLEN 0x4 /* enable clock */ +#define CR_I2CEN 0x2 /* enable I2C */ +#define CR_I2CRST 0x1 /* reset I2C */ +#define CR_ENABLE \ + (CR_ALIEN | CR_SAMIEN | CR_STOPIEN | CR_BERRIEN \ + | CR_DRIEN | CR_DTIEN | CR_SCLEN | CR_I2CEN) + +/* + * REG_STAT + */ +#define SR_CLRAL 0x400 +#define SR_CLRGC 0x200 +#define SR_CLRSAM 0x100 +#define SR_CLRSTOP 0x80 +#define SR_CLRBERR 0x40 +#define SR_DR 0x20 /* DR received one new data byte */ +#define SR_DT 0x10 /* DR trandmitted one new data byte */ +#define SR_BB 0x8 +#define SR_BUSY 0x4 +#define SR_ACK 0x2 +#define SR_RW 0x1 + +/* + * REG_BMR + */ +#define BMR_SCL 0x2 +#define BMR_SDA 0x1 + +#endif /* EOF */